LTC2439-1CGN Linear Technology, LTC2439-1CGN Datasheet - Page 8

• Manufacturer Part Number: LTC2439-1CGN
• Description: IC ADC 16BIT 16CH MCRPWR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC2439-1CGN

• Number Of Bits: 16
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.150", 3.95mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC2439-1
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins
outputting the conversion result and inputting channel
selection bits. Taking CS high at this point will terminate
the data output state and start a new conversion. The
channel selection control bits are shifted in through SDI
from the first rising edge of SCK and depending on the
control bits, the converter updates its channel selection
immediately and is valid for the next conversion. The
details of channel selection control bits are described in
the Input Data Mode section. The output data is shifted out
the SDO pin under the control of the serial clock (SCK). The
output data is updated on the falling edge of SCK allowing
8
SDO
SCK
SDI
CS
SLEEP
Hi-Z
BIT18
EOC
(1)
OPERATION
U
BIT17
(0)
(0)
SDO
SCK
SDI
CONVERSION RESULT
U
EN
BIT16
SIG
ADDRESS
OUTPUT
N – 1
N – 1
N
SGL
BIT15
MSB
W
ODD/
SIGN
BIT14
B22
DON’T CARE
CONVERSION N
Figure 3b. Typical Operation Sequence
Figure 3a. Input/Output Data Timing
A2
BIT13
Hi-Z
U
A1
BIT12
CONVERSON RESULT
CONVERSION RESULT
A0
DATA INPUT/OUTPUT
BIT11
ADDRESS
OUTPUT
N + 1
N
N
the user to reliably latch data on the rising edge of SCK (see
Figure 3). The data output state is concluded once 19 bits
are read out of the ADC or when CS is brought HIGH. The
device automatically initiates a new conversion and the
cycle repeats. In order to maintain compatibility with
24-/32-bit data transfers, it is possible to clock the
LTC2439-1 with additional serial clock pulses. This results
in additional data bits which are always logic HIGH.
Through timing control of the CS and SCK pins, the
LTC2439-1 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
BIT6
CONVERSION N + 1
DON’T CARE
Hi-Z
BIT5
DON’T CARE
BIT4
CONVERSION RESULT
BIT3
ADDRESS
OUTPUT
N + 1
N + 1
N + 2
BIT2
24391 F03b
Hi-Z
BIT1
BIT0
LSB
CONVERSION
24391 F03a
24391fa