LTC1400CS8 Linear Technology, LTC1400CS8 Datasheet - Page 13

• Manufacturer Part Number: LTC1400CS8
• Description: IC A/D CONV 12BIT W/SHTDN 8-SOIC
• Manufacturer: Linear Technology

Specifications of LTC1400CS8

• Number Of Bits: 12
• Sampling Rate (per Second): 400k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 160mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
In the Sleep mode, power consumption is reduced to a
minimum by cutting off the supply to all internal circuitry
including the reference. Figure 12 shows the ways to power
down the LTC1400. The chip can enter the Nap mode by
keeping the CLK signal low and pulsing the CONV signal
twice. For Sleep mode operation, CONV signal should be
pulsed four times while CLK is kept low.
The LTC1400 can be returned to active mode easily. The
rising edge of CLK will wake-up the LTC1400. During the
transition from Sleep mode to active mode, the V
age ramp-up time is a function of the loading conditions.
With a 10μF bypass capacitor, the wake-up time from
Sleep mode is typically 4ms. A REFRDY signal will be
activated once the reference has settled and is ready for
an A/D conversion. This REFRDY bit is output to the D
pin before the rest of the A/D converted code.
S/H STATUS
INTERNAL
CONV
D
CLK
OUT
CLK
D
OUT
SAMPLE
U
U
1
Hi-Z
t
3
t
t
2
6
t
2
t
REFRDY D11
10
4
t
8
W
3
4
V
IH
Figure 13. ADC Digital Timing Diagram
D10
5
U
Figure 14. CLK to D
D9
REF
6
V
V
OH
OL
volt-
D8
OUT
HOLD
t
SAMPLE
t
7
CONV
D7
Digital Interface
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the D
the conversion result in serial form.
Figure 13 shows the digital timing diagram of the LTC1400
during the A/D conversion. The CONV rising edge starts
the conversion. Once initiated, it can not be restarted until
the conversion is completed. If the time from CONV signal
to CLK rising edge is less than t
be delayed by one clock cycle.
The digital output data is updated on the rising edge of the
CLK line. D
system on the rising CLK edge. Data remains valid for a
minimum time of t
capture to occur.
8
D6
OUT
D
CLK
OUT
9
Delay
D5
10
OUT
D4
11
data should be captured by the receiving
D3
10
12
t
t
5
9
after the rising CLK edge to allow
D2
13
D1
14
V
SAMPLE
IH
t
7
t
D0
ACQ
2
, the digital output will
t
15
8
OUT
1400 F14
LTC1400
1
Hi-Z
90%
10%
output provides
2
HOLD
REFRDY
1400 F13
13
1400fa