LTC1400CS8 Linear Technology, LTC1400CS8 Datasheet - Page 7

• Manufacturer Part Number: LTC1400CS8
• Description: IC A/D CONV 12BIT W/SHTDN 8-SOIC
• Manufacturer: Linear Technology

Specifications of LTC1400CS8

• Number Of Bits: 12
• Sampling Rate (per Second): 400k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 160mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Conversion Details
The LTC1400 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit serial output based on a preci-
sion internal reference. The control logic provides easy
interface to microprocessors and DSPs through 3-wire
connections.
A rising edge on the CONV input starts a conversion. At
the start of a conversion the successive approximation
register (SAR) is reset. Once a conversion cycle has begun
it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
capacitor during the acquired phase and the comparator
offset is nulled by the feedback switch. In this acquire
phase, it typically takes 200ns for the sample-and-hold
capacitor to acquire the analog signal. During the convert
phase, the comparator feedback switch opens, putting the
comparator into the compare mode. The input switches
connect C
charge onto the summing junction. This input charge is
successively compared with the binary-weighted charges
supplied by the capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion,
the DAC output balances the A
contents (a 12-bit data word) which represent the input
voltage, are output through the serial pin D
A
IN
SAMPLE
HOLD
SAMPLE
IN
input connects to the sample-and-hold
to ground, injecting the analog input
C
U
SAMPLE
DAC
Figure 1. A
U
V
C
DAC
DAC
IN
IN
Input
input charge. The SAR
W
SAMPLE
S1
–
+
COMP
OUT
U
.
D
1400 F01
OUT
S
A
R
Dynamic Performance
The LTC1400 has excellent high speed sampling capability.
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2a shows a
typical LTC1400 FFT plot.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from DC to half the sampling frequency.
Figure 2a shows a typical spectral content with a 400kHz
sampling rate and a 100kHz input. The dynamic perfor-
mance is excellent for input frequencies up to the Nyquist
limit of 200kHz as shown in Figure 2b.
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement
of the effective resolution of an ADC and is directly related
to the S/(N + D) by the equation:
N
=
Figure 2a. LTC1400 Nonaveraged, 4096 Point FFT
Plot with 100kHz Input Frequency in Bipolar Mode
S N D
/
(
–100
–110
–120
+
–60
6 02
–10
–20
–30
–40
–50
–70
–90
–80
.
0
0
)
f
f
SINAD = 72.5dB
THD = – 82dB
– .
SAMPLE
IN
20
1 76
= 94.824kHz
40
= 400kHz
60
FREQUENCY (kHz)
80 100
120
140
160
LTC1400
180
1400 F02a
200
1400fa
7