LTC1400CS8 Linear Technology, LTC1400CS8 Datasheet - Page 4

IC A/D CONV 12BIT W/SHTDN 8-SOIC

LTC1400CS8

Manufacturer Part Number
LTC1400CS8
Description
IC A/D CONV 12BIT W/SHTDN 8-SOIC
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1400CS8

Number Of Bits
12
Sampling Rate (per Second)
400k
Data Interface
MICROWIRE™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
160mW
Voltage Supply Source
Dual ±
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC1400CS8
Manufacturer:
LT
Quantity:
10 000
Part Number:
LTC1400CS8
Manufacturer:
LINEAR/凌特
Quantity:
20 000
DIGITAL I PUTS A D DIGITAL OUTPUTS
full operating temperature range, otherwise specifications are at T
TI I G CHARACTERISTICS
range, otherwise specifications are at T
LTC1400
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below V
mode) or above V
can handle input currents greater than 40mA below V
unipolar mode) or above V
Note 4: When these pin voltages are taken below V
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 40mA below V
without latch-up. These pins are not clamped to V
Note 5: V
specified.
Note 6: Recommended operating conditions.
SYMBOL
V
I
C
I
I
SYMBOL
f
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
4
OZ
SOURCE
SINK
SAMPLE(MAX)
CONV
ACQ
CLK
CLK
WK(NAP)
1
2
3
4
5
6
7
8
9
10
11
OL
OZ
W
U
CC
= 5V, f
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time
CLK Frequency
CLK Pulse Width
Time to Wake Up from Nap Mode
CLK Pulse Width to Return to Active Mode
CONV↑ to CLK↑ Setup Time
CONV↑ After Leading CLK↑
CONV Pulse Width
Time from CLK↑ to Sample Mode
Aperture Delay of Sample-and-Hold
Minimum Delay Between Conversion
Delay Time, CLK↑ to D
Delay Time, CLK↑ to D
Time from Previous Data Remains Valid After CLK↑
Minimum Time between Nap/Sleep Request to Wake Up Request
CC
PARAMETER
Low Level Output Voltage
Hi-Z Output Leakage D
Hi-Z Output Capacitance D
Output Source Current
Output Sink Current
SAMPLE
, they will be clamped by internal diodes. This product
U
= 400kHz, t
CC
without latch-up.
(Unipolar Mode)
(Bipolar Mode V
OUT
OUT
r
U
= t
OUT
f
Valid
Hi-Z
SS
= 5ns unless otherwise
OUT
(ground for unipolar mode)
A
= 25°C unless otherwise noted. (Note 5)
(Note 7)
CC
SS
SS
SS
.
SS
(ground for unipolar
(ground for unipolar
= –5V)
(Unipolar Mode)
(Bipolar Mode V
(ground for
The
CONDITIONS
V
V
V
V
V
denotes the specifications which apply over the full operating temperature
CC
CC
OUT
OUT
OUT
= 4.75V, I
= 4.75V, I
= 0V to V
= 0V
= V
SS
CC
= –5V)
A
= 25°C unless otherwise noted. (Note 5)
O
O
Note 7: Guaranteed by design, not subject to test.
Note 8: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 9: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 10: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 11: The rising edge of CONV starts a conversion. If CONV returns
low at a bit decision point during the conversion, it can create small errors.
For best performance ensure that CONV returns low either within 120ns
after conversion starts (i.e., before the first bit decision) or after the 14
clock cycle. (Figure 13 Timing Diagram).
Note 12: If this timing specification is not met, the device may not respond
to a request for a conversion. To recover from this condition a NAP
request is required.
CC
= 160μA
= 1.6mA
CONDITIONS
(Note 6)
f
(Note 7)
(Notes 7, 12)
(Note 7)
(Note 11)
(Note 7)
Jitter < 50ps (Note 7)
C
C
C
(Notes 7, 12)
CLK
LOAD
LOAD
LOAD
= 6.4MHz
The
= 20pF
= 20pF
= 20pF
denotes the specifications which apply over the
MIN
MIN
400
0.1
50
50
80
50
14
50
0
0.05
0.10
TYP
–10
TYP
230
200
350
265
235
15
10
80
45
40
40
25
MAX
MAX
±10
300
270
385
355
0.4
2.1
6.4
65
80
80
UNITS
UNITS
1400fa
MHz
mA
mA
kHz
μA
pF
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V

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