LTC1851CFW Linear Technology, LTC1851CFW Datasheet
LTC1851CFW
Specifications of LTC1851CFW
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LTC1851CFW Summary of contents
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... The digital outputs are powered from a separate supply allowing for easy interface to 3V digital logic. Typical power consumption is 40mW at 1.25Msps from a single 5V supply. , LTC and LT are registered trademarks of Linear Technology Corporation. M1 SHDN CS CONVST ...
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... REFOUT 11 REFIN 12 REFCOMP 13 GND GND 16 DIFF /S6 17 OUT A2 /S5 18 OUT A1 /S4 19 OUT 20 A0 /S3 OUT 21 D11/S2 22 D10/S1 23 D9/ 48-LEAD PLASTIC TSSOP T JMAX ORDER PART TOP VIEW NUMBER M1 48 SHDN 47 LTC1851CFW CS 46 LTC1851IFW CONVST DIFF UNI/BIP 38 PGA OGND 33 BUSY PACKAGE = 150 C, = 110 C/W ...
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U CO VERTER CHARACTERISTICS temperature range, otherwise specifications are at T PARAMETER CONDITIONS Resolution (No Missing Codes) Integral Linearity Error (Note 7) Differential Linearity Error Offset Error (Bipolar and Unipolar) (Note 8) Gain = 1 (PGA = 1) REFCOMP 2V ...
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LTC1850/LTC1851 ACCURACY SYMBOL PARAMETER SNR Signal-to-Noise Ratio Unipolar, PGA = 0 Unipolar, PGA = 1 Bipolar, PGA = 0 Bipolar, PGA = 1 S/(N+D) Signal-to-(Noise + Distortion) Ratio Unipolar, PGA = 0 Unipolar, PGA = ...
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W U POWER REQUIRE E TS range, otherwise specifications are at T SYMBOL PARAMETER V Positive Supply Voltage DD OV Output Positive Supply Voltage DD I Positive Supply Current DD P Power Dissipation DISS Power Down Positive Supply Current Nap ...
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LTC1850/LTC1851 CHARACTERISTICS range, otherwise specifications are SYMBOL PARAMETER t WR High Time Setup Time BUSY Delay (or RD) ...
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W U TYPICAL PERFOR A CE CHARACTERISTICS Typical INL, PGA =1, LTC1851 1.00 0.50 0.00 –0.50 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1850/51 G01 Typical INL, PGA = 0, LTC1851 1.00 0.50 0.00 –0.50 –1.00 ...
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LTC1850/LTC1851 W U TYPICAL PERFOR A CE CHARACTERISTICS Distortion vs Input Frequency, Bipolar Mode, PGA = 1 –50 –55 –60 –65 THD –70 –75 –80 –85 3RD HARMONIC –90 2ND HARMONIC –95 –100 10 100 1000 10000 FREQUENCY (kHz) 185051 ...
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W U TYPICAL PERFOR A CE CHARACTERISTICS Channel-to-Channel Isolation (Worst Pair) Bipolar Mode, PGA = 0 110 100 90 LIMIT OF MEASUREMENT INPUT FREQUENCY (Hz) Channel-to-Channel Isolation (Worst Pair), Unipolar Mode, PGA = ...
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LTC1850/LTC1851 CTIO S CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can be used single ended relative to the analog input common pin (COM) or differentially in pairs (CH0 and CH1, ...
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CTIO S D9/S0 (Pin 23, LTC1851): Three-State Digital Data Out- puts. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the end ...
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LTC1850/LTC1851 CTIO S PIN NAME DESCRIPTION CH0 to CH7 Analog Inputs 9 COM Analog Input Common Pin 10 REFOUT 2.5V Reference Output 11 REFIN Reference Buffer Input 12 REFCOMP Reference Buffer Output ...
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U U APPLICATIO S I FOR ATIO The LTC1850/LTC1851 are complete and very flexible data acquisition systems. They consist of a 10-bit/12-bit, 1.25Msps capacitive successive approximation A/D con- verter with a wideband sample-and-hold, a configurable 8-channel analog input multiplexer, an ...
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LTC1850/LTC1851 U U APPLICATIO S I FOR ATIO If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer func- tion can create distortion products at the sum and differ- ...
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... Low distortion. LT1363: 70MHz Voltage Feedback Amplifier. 2.5V to 15V supplies. 7.5mA supply current. Low distortion. LT1364/LT1365: Dual and Quad 70MHz Voltage Feedback Amplifiers. 2.5V to 15V supplies. 7.5mA supply current per amplifier. Low distortion. LinearView is a trademark of Linear Technology Corporation. LTC1850/LTC1851 TM 18501f 15 ...
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LTC1850/LTC1851 U U APPLICATIO S I FOR ATIO LT1468/LT1469: Single and Dual 90MHz Voltage Feed- back Amplifier 15V supplies. 7mA supply current per amplifier. Lowest noise and low distortion. LT1630/LT1631: Dual and Quad 30MHz Rail-to-Rail Volt- age Feedback ...
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U U APPLICATIO S I FOR ATIO the offset applied to the “–” input. For single-ended inputs, this offset should be applied to the COM pin. For differen- tial inputs, the “–” input is dictated by the MUX address. For ...
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LTC1850/LTC1851 U U APPLICATIO S I FOR ATIO Unipolar Transfer Characteristic (UNI/BIP = 0) 1111...1111 1111...1110 1111...1101 1000...0001 1000...0000 0111...1111 0111...1110 0000...0010 0000...0001 0000...0000 INPUT VOLTAGE (V) Bipolar Transfer Characteristic (UNI/BIP = 1) 0111...1111 0111...1110 BIPOLAR ...
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U U APPLICATIO S I FOR ATIO SUPPLY BYPASSING High quality, low series resistance ceramic 10 F bypass capacitors should be used. Surface mount ceramic ca- pacitors provide excellent bypassing in a small board space. Alternatively tantalum capacitors ...
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LTC1850/LTC1851 U U APPLICATIO S I FOR ATIO Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD are both tied low. The falling edge of CONVST starts ...
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U U APPLICATIO S I FOR ATIO CS = LOW t 5 CONVST t 6 BUSY RD DATA Figure 7. Mode 2 CONVST Starts a Conversion. Data is Read LOW RD = CONVST t 6 BUSY ...
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LTC1850/LTC1851 U U APPLICATIO S I FOR ATIO In slow memory mode, the processor applies a logic low CONVST), starting the conversion. BUSY goes low, forcing the processor into a Wait state. The previous conversion result ...
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U U APPLICATIO S I FOR ATIO LOCATION 0000 LOCATION 0001 LOCATION 0010 LOCATION 1110 LOCATION 1111 The sequencer is accessed by taking the M1 mode pin high. With M1 high, the sequencer memory is accessed by taking the M0 ...
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LTC1850/LTC1851 U U APPLICATIO S I FOR ATIO Sequence Run Mode Once the sequencer is programmed taken high. BUSY will also come back high enabling CONVST and the next falling CONVST will begin a conversion using the MUX ...
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U U APPLICATIO S I FOR ATIO W U LTC1850/LTC1851 18501f 25 ...
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LTC1850/LTC1851 U U APPLICATIO S I FOR ATIO 18501f ...
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... DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ...
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... Pin-Compatible, Programmable Multiplexer and Sequencer www.linear.com 0 IDT7202LA15 13 2 8-BIT DATA BUS READ_HIGH_FIFO HIGH_FIFO_EMPTY HIGH_FIFO_HALF_FULL 23 RT HIGH BYTE_FIFO_RETRANSMIT XI GND 7 14 HIGH_FIFO_FULL_FLAG LOW_FIFO_FULL_FLAG FIFO_RESET 0 IDT7202LA15 READ_LOW_FIFO LOW_FIFO_EMPTY LOW_FIFO_HALF_FULL 23 RT LOW BYTE_FIFO_RETRANSMIT XI GND 7 14 18501 TA01 18501f LT/TP 0303 2K • PRINTED IN THE USA LINEAR TECHNOLOGY CORPORATION 2001 ...