AD7276BRMZ Analog Devices Inc, AD7276BRMZ Datasheet
AD7276BRMZ
Specifications of AD7276BRMZ
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AD7276BRMZ Summary of contents
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FEATURES Throughput rate: 3 MSPS Specified for Power consumption 12 MSPS with 3 V supplies Wide input bandwidth 70 dB SNR at 1 MHz input frequency Flexible power/serial clock ...
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AD7276/AD7277/AD7278 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AD7276 Specifications ................................................................. 3 AD7277 Specifications ................................................................. 5 AD7278 Specifications ................................................................. 7 Timing ...
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SPECIFICATIONS AD7276 SPECIFICATIONS Grade and A Grade unless otherwise noted. MAX Table 2. Parameter DYNAMIC PERFORMANCE 4 Signal-to-Noise + Distortion (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) ...
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AD7276/AD7277/AD7278 Parameter CONVERSION RATE Conversion Time 4 Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) 6 Power Dissipation Normal Mode (Operational) Partial Power-Down ...
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AD7277 SPECIFICATIONS MHz SCLK SAMPLE Table 3. Parameter DYNAMIC PERFORMANCE 3 Signal-to-Noise + Distortion (SINAD) 3 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion ...
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AD7276/AD7277/AD7278 Parameter POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) 5 Power Dissipation Normal Mode (Operational) Partial Power-Down Full Power-Down 1 Temperature range from −40°C to +125°C. 2 ...
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AD7278 SPECIFICATIONS MHz SCLK SAMPLE Table 4. Parameter DYNAMIC PERFORMANCE 3 Signal-to-Noise + Distortion (SINAD) 3 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion ...
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AD7276/AD7277/AD7278 Parameter POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) 5 Power Dissipation Normal Mode (Operational) Partial Power-Down Full Power-Down 1 Temperature range from −40°C to +125°C. 2 ...
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SCLK SDATA Figure 2. Access Time After SCLK Falling Edge t 7 SCLK V IH SDATA V IL Figure 3. Hold Time After SCLK Falling Edge SCLK V IH SDATA V IL Figure 4. SCLK Falling Edge SDATA ...
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AD7276/AD7277/AD7278 TIMING EXAMPLES For the AD7276 brought high during the 14 edge after the two leading zeros and 12 bits of the conversion have been provided, the part can achieve the fastest throughput rate, 3 MSPS. If ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 6. Parameters V to GND DD Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies Operating ...
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AD7276/AD7277/AD7278 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V AD7276 AD7277/ GND AD7278 2 5 TOP VIEW (Not to Scale Figure 8. 6-Lead TSOT Pin Configuration Table 7. Pin Function Descriptions Pin No. 6-Lead TSOT ...
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TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A –20 –40 –60 –80 –100 –120 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 FREQUENCY (kHz) Figure 10. AD7276 Dynamic Performance at 3 ...
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AD7276/AD7277/AD7278 –50 – 100Ω –60 IN –65 –70 R –75 –80 –85 –90 100 INPUT FREQUENCY (kHz) Figure 16. THD vs. Analog Input Frequency at 3 MSPS for Various Source Impedances, SCLK Frequency = 48 MHz, Supply Voltage ...
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TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7276/ AD7277/AD7278, the endpoints of the transfer function are zero scale at 0.5 LSB below the first code transition ...
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AD7276/AD7277/AD7278 THEORY OF OPERATION CIRCUIT INFORMATION The AD7276/AD7277/AD7278 are fast, micropower, 12-/10-/ 8-bit, single-supply ADCs, respectively. The parts can be operated from a 2. 3.6 V supply. When operated from a supply voltage within this range, the AD7276/AD7277/AD7278 ...
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The load regulation of the REF193 is typically 10 ppm/mA (REF193 V), which results in an error of 50 ppm (150 μV) S for the 5 mA drawn from it. When from the ...
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AD7276/AD7277/AD7278 MODES OF OPERATION The mode of operation of the AD7276/AD7277/AD7278 is selected by controlling the logic state of the conversion. There are three possible modes of operation: normal mode, partial power-down mode, and full power-down mode. The point at ...
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To exit this mode of operation and power up the AD7276/ AD7277/AD7278, users should perform a dummy conversion. On the falling edge of , the device begins to power up and CS continues to power up as long as is ...
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AD7276/AD7277/AD7278 THE PART BEGINS TO POWER SCLK A SDATA INVALID DATA THE PART ENTERS PARTIAL POWER-DOWN SCLK INVALID DATA SDATA THE PART BEGINS TO POWER SCLK SDATA INVALID DATA THE PART ...
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POWER VS. THROUGHPUT RATE Figure 29 shows the power consumption of the device in normal mode, in which the part is never powered down. By using the power-down mode of the AD7276/AD7277/AD7278 when not performing a conversion, the average power ...
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AD7276/AD7277/AD7278 SERIAL INTERFACE Figure 31 through Figure 34 show the detailed timing diagrams for serial interfacing to the AD7276, AD7277, and AD7278. The serial clock provides the conversion clock and controls the transfer of information from the AD7276/AD7277/AD7278 during conversion. ...
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CS t CONVERT SCLK t 3 SDATA Z ZERO DB11 DB10 THREE- STATE 2 LEADING ZEROS Figure 32. AD7276 Serial Interface Timing Diagram 16 SCLK Cycle CS t CONVERT SCLK ...
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AD7276/AD7277/AD7278 AD7278 SCLK CYCLE SERIAL INTERFACE For the AD7278 brought high during the 10 edge after the two leading zeros and eight bits of the conversion are provided, then the part can achieve a ...
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APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7276/AD7277/ AD7278 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This design facilitates using ground planes ...
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AD7276/AD7277/AD7278 OUTLINE DIMENSIONS 1.60 BSC PIN 1 INDICATOR * 0.90 0.87 0.84 0.10 MAX 3.20 3.00 2.80 IDENTIFIER 0.95 0.85 0.75 COPLANARITY 2.90 BSC 2.80 BSC 0.95 BSC 1.90 BSC 0.20 * 1.00 MAX ...
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... ORDERING GUIDE Temperature Model Range AD7276BRM −40°C to +125°C 2 AD7276BRMZ −40°C to +125°C AD7276BRMZ-REEL 2 −40°C to +125°C 2 AD7276BUJZ-REEL7 −40°C to +125°C 2 AD7276BUJZ-500RL7 −40°C to +125° AD7276YUJZ-500RL7 −40°C to +125° AD7276YUJZ-REEL7 −40°C to +125°C 2 AD7276ARMZ − ...
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AD7276/AD7277/AD7278 NOTES ©2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04903-0-11/09(B) Rev Page ...