AD7276BRMZ Analog Devices Inc, AD7276BRMZ Datasheet - Page 24

• Manufacturer Part Number: AD7276BRMZ
• Description: IC ADC 12BIT 3MSPS HS LP 8MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7276BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Number Of Converters: 1
• Power Dissipation (max): 19.8mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 3MSPS
• Input Channel Type: Single Ended
• Supply Current: 5.5mA
• Digital Ic Case Style: SOP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7276CBZ - BOARD EVALUATION FOR AD7276
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7276/AD7277/AD7278
AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE
For the AD7278, if CS is brought high during the 10
edge after the two leading zeros and eight bits of the conversion
are provided, then the part can achieve a 4 MSPS throughput
rate. For the AD7278, the track-and-hold goes back into track
mode on the ninth rising edge. In this case, a f
throughput of 4 MSPS result in a cycle time of t
t
satisfies the requirement of 60 ns for t
t
This allows a value of 43 ns for t
requirement of 4 ns.
MICROPROCESSOR INTERFACING
AD7276/AD7277/AD7278-to-ADSP-BF53x
The ADSP-BF53x family of DSPs interfaces directly to the
AD7276/AD7277/AD7278 without requiring glue logic. The
SPORT0 Receive Configuration 1 Register should be set up as
outlined in Table 9.
ACQ
ACQ
= 250 ns, where t
comprises 0.5(1/f
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7278*
AD7276/
AD7277/
Figure 36. Interfacing with ADSP-BF53x
DOUT
SCLK
DIN
2
CS
= 6 ns minimum and t
SCLK
) + t
8
+ t
QUIET
QUIET
, satisfying the minimum
ACQ
, where t
SPORT0
RCLK0
DR0PRI
RFS0
DT0
ADSP-BF53x*
.
Figure 35
ACQ
SCLK
2
+ 8.5(1/f
= 67 ns. This
8
= 48 MHz and
= 14 ns max.
shows that
th
rising
SCLK
) +
Rev. B | Page 24 of 28
Table 9. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
Setting
RCKFE = 1
LRFS = 1
RFSR = 1
IRFS = 1
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
TFSR = RFSR = 1
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
Active low frame signal
Internal receive clock
Receive enabled
Description
Sample data with falling edge of RSCLK
Frame every word
Internal RFS used
Receive MSB first
Zero fill
16-bit data-word (or can be set to 1101 for
14-bit data-word)