AD9255BCPZ-80 Analog Devices Inc, AD9255BCPZ-80 Datasheet - Page 34

• Manufacturer Part Number: AD9255BCPZ-80
• Description: IC ADC 14BIT 80MSPS 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9255BCPZ-80

• Data Interface: Serial, SPI™
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Number Of Converters: 1
• Power Dissipation (max): 248mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 80MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9255
SERIAL PORT INTERFACE (SPI)
The AD9255 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to, or read from, via the port. Memory is organized
into bytes that can be further divided into fields, which are docu-
mented in the Memory Map section. For detailed operational
information, see AN-877Application Note, Interfacing to High
Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK/DFS pin, the
SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS
(a serial clock) is used to synchronize the read and write data
presented from and to the ADC. The SDIO/DCS (serial data
input/output) is a dual-purpose pin that allows data to be sent
and read from the internal ADC memory map registers. The
CSB (chip select bar) is an active low control that enables or
disables the read and write cycles.
Table 14. Serial Port Interface Pins
Pin Mnemonic
SCLK/DFS
SDIO/DCS
CSB
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. See Figure 84
and Table 5 for an example of the serial timing and its definitions.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes
to allow for additional external timing. When CSB is tied high
at power-up, SPI functions are placed in high impedance mode.
This mode turns on any SPI pin secondary functions. When
CSB is toggled low after power-up, the part remains in SPI
mode and does not revert back to pin mode.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
Function
Serial clock. The SCLK function of the pin is for
the serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO is the serial data input/output function
of the pin. A dual-purpose pin that typically
serves as an input or an output, depending on
the instruction being sent and the relative
position in the timing frame.
Chip select bar. An active low control that
gates the read and write cycles.
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All data is composed of 8-bit words. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. This allows the serial
data input/output (SDIO) pin to change direction from an input
to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 14 comprise the physical interface
between the user programming device and the serial port of the
AD9255. When using the SPI interface, the SCLK pin and the
CSB pin function as inputs. The SDIO pin is bidirectional, func-
tioning as an input during write phases and as an output during
readback.
The AD9255 has a separate supply pin for the SPI interface, SVDD.
The SVDD pin can be set at any level between 1.8 V and 3.3 V
to enable operation with a SPI bus at these voltages without
requiring level translation. If the SPI port is not used, SVDD
can be tied to the DRVDD voltage.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in AN-812 Application Note, Microcontroller-
Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9255 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are tied to AVDD or ground during
device power-on, they are associated with a specific function.
The Digital Outputs section describes the alternate functions
that are supported on the AD9255.