AD6654BBC Analog Devices Inc, AD6654BBC Datasheet - Page 54

• Manufacturer Part Number: AD6654BBC
• Description: IC ADC 14BIT W/6CH RSP 256CSPBGA
• Manufacturer: Analog Devices Inc

Specifications of AD6654BBC

• Number Of Bits: 14
• Sampling Rate (per Second): 92.16M
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 2.5W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-CSPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6654
When an output data sample is available for output from an
AGC, the parallel port initiates the transfer by pulling the
PxREQ signal high. In response, the processor receiving the
data needs to pull the PxACK signal high, acknowledging that it
is ready to receive the signal. In Figure 59, the PxACK is already
pulled high and, therefore, the 8-bit I data and 8-bit Q data are
simultaneously output on the data bus on the next PCLK rising
edge after PxREQ is driven logic high. The PxIQ signal also
goes high to indicate that I/Q data is available on the data bus.
When I/Q data is being output, the channel indicator pins
PxCH[2:0] indicate the data source (AGC number).
Figure 59 is the timing diagram for parallel I/Q mode with the
AGC gain word disabled. Figure 60 is a similar timing diagram
with the AGC gain word enabled. In the PCLK cycle after the
PxCH [2:0]
Px [15:0]
PxGAIN
PxACK
PxREQ
PCLK
PxIQ
PxCH [2:0]
Px [15:0]
PxGAIN
PxACK
PxREQ
PCLK
PxIQ
Figure 58. Interleaved I/Q Mode with an AGC Gain Word
Figure 59. Parallel I/Q Mode Without an AGC Gain Word
t
DPREQ
Rev. 0 | Page 54 of 88
t
t
t
t
DPP
DPIQ
DPREQ
DPCH
I[15:0]
LOGIC LOW 0
I/Q data, the AGC gain word is output on the data bus, and the
PxGAIN signal is pulled high to indicate that the gain word is
available on the parallel port. During this PCLK cycle, the PxIQ
signal is pulled low to indicate that I/Q data is not available on
the data bus. Therefore, in parallel I/Q mode, a minimum of
two PCLK cycles is required to output one sample of output
data on the parallel port without and with the AGC gain word,
respectively.
The order of data output is dependent on when data arrives at
the port, which is a function of total decimation rate, DRCF/
CRCF decimation phase, and start hold-off values. Priority
order from highest to lowest is, AGC0, AGC1, AGC2, AGC3,
AGC4, and AGC5 for both parallel I/Q and interleaved modes
of output.
PxCH [2:0] = CHANNEL #
PxCH [2:0] =
t
t
DPP
Q [15:8]
t
DPIQ
AGC NO.
Q[15:0]
DPCH
I [15:8]
GAIN [11:0]
t
DPGAIN
0000 +