AD5293BRUZ-20 Analog Devices Inc, AD5293BRUZ-20 Datasheet - Page 10

• Manufacturer Part Number: AD5293BRUZ-20
• Description: IC DGTL POT 1024POS 20K 14TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5293BRUZ-20

• Temperature Coefficient: 35 ppm/°C Typical
• Taps: 1024
• Resistance (ohms): 20K
• Number Of Circuits: 1
• Interface: SPI Serial
• Voltage - Supply: 9 V ~ 33 V, ±9 V ~ 16.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 20K
• End To End Resistance: 20kohm
• Track Taper: Linear
• No. Of Steps: 256
• Resistance Tolerance: ± 1%
• Control Interface: Serial, SPI
• No. Of Pots: Single
• Potentiometer Ic: RoHS Compliant
• Supply Voltage Range: ± 9V To ± 16.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD5293BRUZ-20-U1; AD5293BRUZ-20-U1

AD5293
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
RESET
V
A
W
B
V
EXT_CAP
V
GND
DIN
SCLK
SYNC
SDO
RDY
SS
DD
LOGIC
Description
Hardware Reset Pin. Sets the RDAC register to midscale. RESET is activated at the logic high transition. Tie RESET to
V
Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF ceramic
capacitors and 10 μF capacitors.
Terminal A of RDAC. V
Wiper Terminal W of RDAC. V
Terminal B of RDAC. V
Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V.
Logic Power Supply, 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
Ground Pin, Logic Ground Reference.
Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be
transferred at rates up to 50 MHz.
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes
low, it enables the shift register, and data is transferred in on the falling edges of the following clocks. The selected
register is updated on the rising edge of SYNC, following the 16
16
Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data
from the serial register in daisy-chain mode or in readback mode.
Ready Pin. This active-high, open-drain output identifies the completion of a write or read operation to or from
the RDAC register.
LOGIC
th
clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
if not used.
SS
SS
≤ V
≤ V
B
A
≤ V
≤ V
EXT_CAP
SS
≤ V
RESET
DD
DD
V
V
.
.
W
Figure 5. Pin Configuration
DD
SS
W
A
B
≤ V
Rev. D | Page 10 of 24
1
2
3
4
5
6
7
DD
Not to Scale
.
AD5293
TOP VIEW
14
13
12
11
10
9
8
RDY
SDO
SYNC
SCLK
DIN
GND
V
LOGIC
th
clock cycle. If SYNC is taken high before the