AD5293BRUZ-20 Analog Devices Inc, AD5293BRUZ-20 Datasheet - Page 21

• Manufacturer Part Number: AD5293BRUZ-20
• Description: IC DGTL POT 1024POS 20K 14TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5293BRUZ-20

• Temperature Coefficient: 35 ppm/°C Typical
• Taps: 1024
• Resistance (ohms): 20K
• Number Of Circuits: 1
• Interface: SPI Serial
• Voltage - Supply: 9 V ~ 33 V, ±9 V ~ 16.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 20K
• End To End Resistance: 20kohm
• Track Taper: Linear
• No. Of Steps: 256
• Resistance Tolerance: ± 1%
• Control Interface: Serial, SPI
• No. Of Pots: Single
• Potentiometer Ic: RoHS Compliant
• Supply Voltage Range: ± 9V To ± 16.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD5293BRUZ-20-U1; AD5293BRUZ-20-U1

PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B terminal and wiper-to-A terminal that is proportional
to the input voltage at A to B, as shown in Figure 48. Unlike the
polarity of V
A to B, W to A, and W to B can be at either polarity.
If ignoring the effect of the wiper resistance for simplicity,
connecting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B that
ranges from 0 V to 30 V − 1 LSB. Each LSB of voltage is equal to
the voltage applied across the A terminal and B terminal, divided
by the 1024 positions of the potentiometer divider. The general
equation defining the output voltage at V
ground for any valid input voltage applied to Terminal A and
Terminal B, is
To optimize the wiper position update rate when in voltage
divider mode, it is recommended that the internal ±1% resistor
tolerance calibration feature be disabled by programming Bit C2
of the control register (see Table 11).
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
rheostat mode, the output voltage is dependent mainly on the ratio
of the internal resistors, R
values. Therefore, the temperature drift reduces to 5 ppm/°C.
EXT_CAP CAPACITOR
A 1 μF capacitor to GND must be connected to the EXT_CAP
pin (see Figure 49) on power-up and throughout the operation
of the AD5293. This capacitor must have a voltage rating of ≥7 V.
V
W
(
D
)
=
Figure 49. Hardware Setup for the EXT_CAP Pin
DD
Figure 48. Potentiometer Mode Configuration
1024
to GND, which must be positive, voltage across
D
1µF
C1
×
V
V
A
IN
+
WA
1024
EXT_CAP
and R
1024
A
B
AD5293
−
GND
W
D
WB
×
, and not on the absolute
V
V
OUT
B
W
, with respect to
Rev. D | Page 21 of 24
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TERMINAL VOLTAGE OPERATING RANGE
The positive V
define the boundary conditions for proper 3-terminal, digital
potentiometer operation. Supply signals present on the A, B,
and W terminals that exceed V
internal forward-biased diodes (see Figure 50).
The ground pin of the AD5293 is primarily used as a digital
ground reference. To minimize the digital ground bounce, the
AD5293 ground pin should be joined remotely to common ground.
The digital input control signals to the AD5293 must be referenced
to the device ground pin (GND) to satisfy the logic level defined
in the Specifications section.
Power-Up Sequence
Because there are diodes to limit the voltage compliance at the
A, B, and W terminals (see Figure 50), it is important to power
V
terminals. Otherwise, the diode is forward-biased such that V
and V
sequence is GND, V
V
digital inputs is not important, as long as they are powered after
V
Regardless of the power-up sequence and the ramp rates of the
power supplies, the power-on preset activates after V
powered, restoring midscale to the RDAC register.
DD
A
DD
, V
, V
and V
B
SS
, and V
SS
are powered up unintentionally. The ideal power-up
Figure 50. Maximum Terminal Voltages Set by V
, and V
SS
first, before applying any voltage to the A, B, and W
W
DD
. The order of powering up V
LOGIC
and negative V
.
SS
, V
LOGIC
, V
SS
DD
DD
power supplies of the AD5293
or V
, the digital inputs, and then
SS
are clamped by the
A
, V
B
, V
V
A
W
B
V
DD
DD
SS
and V
W
, and the
AD5293
LOGIC
SS
is
DD