AD5254BRUZ50 Analog Devices Inc, AD5254BRUZ50 Datasheet - Page 18
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AD5254BRUZ50
Manufacturer Part Number
AD5254BRUZ50
Description
IC POT DGTL QUAD 50K 20TSSOP
Manufacturer
Analog Devices Inc
Datasheet
1.AD5254BRUZ100.pdf
(32 pages)
Specifications of AD5254BRUZ50
Memory Type
Non-Volatile
Temperature Coefficient
650 ppm/°C Typical
Taps
256
Resistance (ohms)
50K
Number Of Circuits
4
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Resistance In Ohms
50K
End To End Resistance
50kohm
Track Taper
Linear
Resistance Tolerance
± 30%
No. Of Steps
256
No. Of Pots
Quad
Potentiometer Ic Case
RoHS Compliant
Supply Voltage Range
± 2.25V To ± 2.75V
Control Interface
I2C, Serial
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD5254EVAL - BOARD EVAL FOR AD5254
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5254BRUZ50
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD5253/AD5254
RDAC/EEMEM Quick Commands
The AD5253/AD5254 feature 12 quick commands that facilitate
easy manipulation of RDAC wiper settings and provide RDAC-
to-EEMEM storing and restoring functions. The command
format is shown in Figure 31, and the command descriptions
are shown in Table 9.
When using a quick command, issuing a third byte is not
needed, but is allowed. The quick commands reset and store
RDAC to EEMEM require acknowledge polling to determine
whether the command has finished executing.
R
The AD5253/AD5254 feature patented R
the nonvolatile memory. The tolerance of each channel is stored
in the memory during the factory production and can be read
by users at any time. The knowledge of the stored tolerance,
which is the average of R
users to predict R
precision, rheostat mode, and open-loop applications, in which
knowledge of absolute resistance is critical.
The stored tolerances reside in the read-only memory and are
expressed as percentages. Each tolerance is 16 bits long and is
stored in two memory locations (see Table 10). The tolerance
data is expressed in sign magnitude binary format stored in two
bytes; an example is shown in Figure 32 . For the first byte in
Register N, the MSB is designated for the sign (0 = + and 1 = –)
and the 7 LSB is designated for the integer portion of the
tolerance. For the second byte in Register N + 1, all eight data
Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/ REG = 1, A2 = 0)
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
:
:
1
1
This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.
AB
Tolerance Stored in Read-Only Memory
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
:
:
1
AB
accurately. This feature is valuable for
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
:
:
1
AB
over all codes (see Figure 16), allows
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
:
:
1
AB
tolerances storage in
Command Description
NOP
Restore EEMEM (A1, A0) to RDAC (A1, A0)
Store RDAC (A1, A0) to EEMEM (A1, A0)
Decrement RDAC (A1, A0) 6 dB
Decrement all RDACs 6 dB
Decrement RDAC (A1, A0) one step
Decrement all RDACs one step
Reset: restore EEMEMs to all RDACs
Increment RDACs (A1, A0) 6 dB
Increment all RDACs 6 dB
Increment RDACs (A1, A0) one step
Increment all RDACs one step
Reserved
:
:
Reserved
Rev. B | Page 18 of 32
bits are designated for the decimal portion of tolerance. As
shown in Table 10 and Figure 32, for example, if the rated R
10 kΩ and the data readback from Address 11000 shows 0001
1100 and Address 11001 shows 0000 1111, then RDAC0
tolerance can be calculated as
MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2
Tolerance = 28.06% and, therefore,
R
EEMEM Write-Acknowledge Polling
After each write operation to the EEMEM registers, an internal
write cycle begins. The I
determine if the internal write cycle is complete and the I
interface is enabled, interface polling can be executed. I
interface polling can be conducted by sending a start condition
followed by the slave address and the write bit. If the I
interface responds with an ACK, the write cycle is complete and
the interface is ready to proceed with further operations. Other-
wise, I
Command 2 and Command 7 also require acknowledge polling.
EEMEM Write Protection
Setting the WP pin to logic low after EEMEM programming
protects the memory and RDAC registers from future write
operations. In this mode, the EEMEM and RDAC read
operations function as normal.
AB_ACTUAL
2
C interface polling can be repeated until it succeeds.
= 12.806 kΩ
1
2
C interface of the device is disabled. To
–8
= 0.06
2
C
2
C
2
C
AB
is