AD5254BRUZ50 Analog Devices Inc, AD5254BRUZ50 Datasheet - Page 22
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AD5254BRUZ50
Manufacturer Part Number
AD5254BRUZ50
Description
IC POT DGTL QUAD 50K 20TSSOP
Manufacturer
Analog Devices Inc
Datasheet
1.AD5254BRUZ100.pdf
(32 pages)
Specifications of AD5254BRUZ50
Memory Type
Non-Volatile
Temperature Coefficient
650 ppm/°C Typical
Taps
256
Resistance (ohms)
50K
Number Of Circuits
4
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Resistance In Ohms
50K
End To End Resistance
50kohm
Track Taper
Linear
Resistance Tolerance
± 30%
No. Of Steps
256
No. Of Pots
Quad
Potentiometer Ic Case
RoHS Compliant
Supply Voltage Range
± 2.25V To ± 2.75V
Control Interface
I2C, Serial
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD5254EVAL - BOARD EVAL FOR AD5254
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5254BRUZ50
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD5253/AD5254
DIGITAL INPUT/OUTPUT CONFIGURATION
SDA is a digital input/output with an open-drain MOSFET that
requires a pull-up resistor for proper communication. On the
other hand, SCL and WP are digital inputs for which pull-up
resistors are recommended to minimize the MOSFET cross-
conduction current when the driving signals are lower than
V
Figure 35
WP can be permanently tied to V
the write-protect feature is not used. If WP is left floating, an
internal current source pulls it low to enable write protection. In
applications in which the device is programmed infrequently,
this allows the part to default to write-protection mode after
any one-time factory programming or field calibration without
using an on-board pull-down resistor. Because there are
protection diodes on all inputs, the signal levels must not be
greater than V
DD
. SCL and WP have ESD protection diodes, as shown in
and
SCL
WP
Figure 36
DD
Figure 36. Equivalent WP Digital Input
to prevent forward biasing of the diodes.
INPUTS
Figure 35. SCL Digital Input
.
GND
GND
DD
without a pull-up resistor if
V
V
DD
DD
Rev. B | Page 22 of 32
MULTIPLE DEVICES ON ONE BUS
The AD5253/AD5254 are equipped with two addressing pins,
AD1 and AD0, that allow up to four AD5253/AD5254 devices
to be operated on one I
AD1 and AD0 on each device must first be defined. An example
is shown in Table 12 and Figure 37. In I
device is issued a different slave address—01011(AD1)(AD0)—
to complete the addressing.
Table 12. Multiple Devices Addressing
AD1
0
0
1
1
In wireless base station smart-antenna systems that require
arrays of digital potentiometers to bias the power amplifiers,
large numbers of AD5253/AD5254 devices can be addressed by
using extra decoders, switches, and I/O buses, as shown in
Figure 38. For example, to communicate to a total of 16 devices,
four decoders and 16 sets of combinational switches (four sets
shown in Figure 38) are needed. Two I/O buses serve as the
common inputs of the four 2 × 4 decoders and select four sets
of outputs at each combination. Because the four sets of
combination switch outputs are unique, as shown in Figure 38,
a specific device is addressed by properly programming the I
with the slave address defined as 01011(AD1)(AD0). This
operation allows one of 16 devices to be addressed, provided
that the inputs of the two decoders do not change states. The
inputs of the decoders are allowed to change once the operation
of the specified device is completed.
MASTER
Figure 37. Multiple AD5253/AD5254 Devices on a Single Bus
SDA
AD5253/
AD5254
AD1
AD0
R
AD0
0
1
0
1
SCL
P
R
P
5V
2
C bus. To achieve this result, the states of
SDA
AD5253/
AD5254
AD1
AD0
Device Addressed
U1
U2
U3
U4
SCL
5V
5V
AD5253/
AD5254
SDA
AD1
AD0
2
C programming, each
SCL
5V
SDA
AD5253/
AD5254
AD1
AD0
SCL
SDA
SCL
2
C