ISL95811UFUZ Intersil, ISL95811UFUZ Datasheet - Page 11

• Manufacturer Part Number: ISL95811UFUZ
• Description: IC POT 256TAPS 5BYTES 8-MSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL95811UFUZ

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 4 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 17). On power-up of the ISL95811, the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL95811 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 17). A START condition is ignored during the
power-up sequence and during internal non-volatile write
cycles.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 17). A STOP condition at the end
of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte initiates an internal non-volatile write cycle. The device
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
SDA OUTPUT FROM
SDA OUTPUT FROM
TRANSMITTER
SCL FROM
RECEIVER
SDA
SCL
MASTER
11
START
FIGURE 17. VALID DATA CHANGES, START, AND STOP CONDITIONS
START
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
1
STABLE
DATA
ISL95811
CHANGE
DATA
enters its standby state when the internal non-volatile write
cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting 8 bits. During the ninth clock cycle, the receiver
pulls the SDA line LOW to acknowledge the reception of the
8 bits of data (see Figure 18).
The ISL95811 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL95811 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 0101000 as the seven
MSBs. The LSB is the Read/Write bit. Its value is “1” for a
Read operation and “0” for a Write operation (see Table 4).
(MSB)
0
STABLE
DATA
TABLE 4. IDENTIFICATION BYTE FORMAT
1
8
0
1
HIGH IMPEDANCE
STOP
ACK
9
0
0
0
October 6, 2008
FN6759.1
(LSB)
R/W