TWR-K60N512-KEIL Freescale Semiconductor, TWR-K60N512-KEIL Datasheet - Page 143

• Manufacturer Part Number: TWR-K60N512-KEIL
• Description: K60N512 Keil Tower Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K60N512-KEIL

• Rohs Compliant: YES
• Contents: 4 Boards, Documentation, DVD
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Freescale Tower System, K60N512

UART3 is used as the serial port to interface to HyperTerminal, and CAN1 is used to
interface to the CAN bus. The HyperTerminal communication setup is:
The example codes for SCI2CAN are available from the Freescale Web site
www.freescale.com.
15.2.1 FlexCAN initialization
Enable the clock to the FlexCAN module before accessing its registers.
The following steps are performed before initializing the FlexCAN module:
15.2.1.1 Code example and explanation
The following code snippet shows how to enable ERCLK clock:
// Must enable ERCLK
OSC_CR |= OSC_CR_ERCLKEN_MASK;
Clock gating code for all ports and FlexCAN:
// Enable clocks to all ports for pin muxing configuration later
SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK
Configure NVIC to enable corresponding interrupts for FlexCAN:
Freescale Semiconductor
1. Initialize MCG and OSC to enable PLL and ERCLK.
2. Initialize the clock gating in SIM to enable clocks to the FlexCAN module(s) and the
3. Configure the corresponding port pins for FlexCAN through port control.
• Baud rate: 115200
• Data: 8 bit
• Parity: None
• Stop: 1 bit
• Flow control: none
corresponding ports whose pins are to function as FlexCAN pins.
if(isCAN0)
{
}
else
{
}
SIM_SCGC6 |=
SIM_SCGC3 |= SIM_SCGC3_FLEXCAN1_MASK;
| SIM_SCGC5_PORTB_MASK
| SIM_SCGC5_PORTC_MASK
| SIM_SCGC5_PORTD_MASK
| SIM_SCGC5_PORTE_MASK );
SIM_SCGC6_FLEXCAN0_MASK;
Kinetis Quick Reference User Guide, Rev. 0, 11/2010
Chapter 15 FlexCAN Module
143