TWR-K60N512-KEIL Freescale Semiconductor, TWR-K60N512-KEIL Datasheet - Page 45

• Manufacturer Part Number: TWR-K60N512-KEIL
• Description: K60N512 Keil Tower Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K60N512-KEIL

• Rohs Compliant: YES
• Contents: 4 Boards, Documentation, DVD
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Freescale Tower System, K60N512

// set the VDIV field to 0, which is x24, giving 4 x 24
// the PLLS bit is set to enable the PLL
// the clock monitor is enabled, CME=1 to cause a reset if crystal fails
// LOLIE can be optionally set to enable the loss of lock interrupt
// wait until the source of the PLLS clock has switched to the PLL
// wait until the PLL has achieved lock
// set up the SIM clock dividers BEFORE switching to the PLL to ensure the
// system clock speeds are in spec.
// core = PLL (96MHz), bus = PLL/2 (48MHz), flexbus = PLL/2 (48MHz), flash = PLL/4 (24MHz)
// Transition into PEE by setting CLKS to 0
// previous MCG_C1 settings remain the same, just need to set CLKS to 0
// Wait for MCGOUT to switch over to the PLL
// The USB clock divider in the System Clock Divider Register 2 (SIM_CLKDIV2)
// should be configured to generate the 48 MHz USB clock before configuring
// the USB module.
4.3.2 Transitioning between PLL engaged external mode and
To be able to move the MCU into the VLPR (or wait) mode, the MCG must be set in a
low-power, low-frequency mode with MCGCLKOUT <= 2 MHz. This mode is provided
by means of selecting the fast IRC when the MCG is set in BLPI mode. This example
shows how to move to this clock mode from PLL engaged external mode before entering
VLPR and then returns to that mode after VLPR is exited. In VLPR mode, the system
clock dividers cannot be changed. These dividers should be configured when the MCG is
in BLPI mode before the MCU power mode is changed to VLPR.
4.3.2.1 Code example and explanation
// Moving from PEE to BLPI
// first move from PEE to PBE
// Wait for clock status bits to update indicating clock has switched
// now move to FBE mode
// make sure the FRDIV is configured to keep the FLL reference within spec.
Freescale Semiconductor
MCG_C6 = MCG_C6_CME_MASK | MCG_C6_PLLS_MASK;
while (!(MCG_S & MCG_S_PLLST_MASK)){}
while (!(MCG_S & MCG_S_LOCK_MASK)){}
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1)
MCG_C1 &= ~MCG_C1_CLKS_MASK;
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){}
MCG_C1 |= MCG_C1_CLKS(2); // select external reference clock as MCG_OUT
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
MCG_C1 &= ~MCG_C1_FRDIV_MASK; // clear FRDIV field
MCG_C1 |= MCG_C1_FRDIV(3); // set FLL ref divider to 256
MCG_C6 &= ~MCG_C6_PLLS_MASK; // clear PLLS to select the FLL
while (MCG_S & MCG_S_PLLST_MASK){} // Wait for PLLST status bit to clear to
SIM_CLKDIV2 |= SIM_CLKDIV2_USBDIV(1); // sets USB divider to /2 assuming reset
bypassed low power internal mode
| SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(3);
Kinetis Quick Reference User Guide, Rev. 0, 11/2010
// state of the SIM_CLKDIV2 register
= 96 MHz
Chapter 4 Clocking System
45