CAT5409YI-50-T2 ON Semiconductor, CAT5409YI-50-T2 Datasheet - Page 8

• Manufacturer Part Number: CAT5409YI-50-T2
• Description: IC POT DPP QUAD 64TAP I2C 24TSSO
• Manufacturer: ON Semiconductor

Specifications of CAT5409YI-50-T2

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Bus Protocol
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5409 will be considered a slave device
in all applications.
START Condition
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT5409 monitors the SDA and
SCL lines and will not respond until this condition is met.
STOP Condition
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
START condition. The Master then sends the address of the
particular slave device it is requesting. The four most
Write Operations
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the requested
operation of CAT5409. The instruction byte consist of a
four−bit opcode followed by two register selection bits and
two pot selection bits. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the selected register. The CAT5409
acknowledges once more and the Master generates the
STOP condition, at which time if a non−volatile data register
is being selected, the device begins an internal programming
cycle to non−volatile memory. While this internal cycle is in
The following defines the features of the I
The device controlling the transfer is a master, typically a
The START Condition precedes all commands to the
A LOW to HIGH transition of SDA when SCL is HIGH
The bus Master begins a transmission by sending a
In the Write mode, the Master device sends the START
1. Data transfer may be initiated only when the bus is
2. During a data transfer, the data line must remain
not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
FROM TRANSMITTER
FROM RECEIVER
DATA OUTPUT
DATA OUTPUT
SCL FROM
MASTER
START
2
C bus protocol:
Figure 5. Acknowledge Timing
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8
significant bits of the 8−bit slave address are fixed as 0101
for the CAT5409 (see Figure 6). The next four significant
bits (A3, A2, A1, A0) are the device address bits and define
which device the Master is accessing. Up to sixteen devices
may be individually addressed by the system. Typically,
+5 V and ground are hard−wired to these pins to establish the
device’s address.
address byte, the CAT5409 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
Acknowledge
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5409 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
progress, the device will not respond to any request from the
Master device.
Acknowledge Polling
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation, the
CAT5409 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address. If the CAT5409 is
still busy with the write operation, no ACK will be returned.
If the CAT5409 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.
After the Master sends a START condition and the slave
After a successful data transfer, each receiving device is
The CAT5409 responds with an acknowledge after
When the CAT5409 is in a READ mode it transmits 8 bits
The disabling of the inputs can be used to take advantage
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ACKNOWLEDGE
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