CAT5409YI-50-T2 ON Semiconductor, CAT5409YI-50-T2 Datasheet - Page 9

• Manufacturer Part Number: CAT5409YI-50-T2
• Description: IC POT DPP QUAD 64TAP I2C 24TSSO
• Manufacturer: ON Semiconductor

Specifications of CAT5409YI-50-T2

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write Protection
against inadvertent programming of the non−volatile data
registers. If the WP pin is tied to LOW, the data registers are
protected and become read only. Similarly, the WP pin going
low after start but after start will interrupt non−volatile write
Instruction and Register Description
Slave Address Byte
processor is called the Slave/DPP Address Byte. The most
significant four bits of the Device Type address are a device
type identifier. These bits for the CAT5409 are fixed at
0101[B] (refer to Figure 8).
and must match the physical device address which is defined
by the state of the A3 − A0 input pins for the CAT5409 to
successfully continue the command sequence. Only the
device which slave address matches the incoming device
address sent by the master executes the instruction. The A3
− A0 inputs can be actively driven by CMOS input signals
or tied to V
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
The Write Protection feature allows the user to protect
The first byte sent to the CAT5409 from the master/
The next four bits, A3 − A0, are the internal slave address
CC
or V
(MSB)
(MSB)
ID3
SS
BUS ACTIVITY:
I3
0
.
SDA LINE
MASTER
CAT5409
ID2
I2
1
Device Type
Identifier
Instruction
S
T
A
R
T
Opcode
S
Fixed Variable
SLAVE/DPP
ADDRESS
0
Figure 8. Identification Byte Format
ID1
Figure 9. Instruction Byte Format
I1
0
Figure 6. Slave Address Bits
1
Figure 7. Write Timing
http://onsemi.com
0
A
C
K
ID0
INSTRUCTION
I0
1
1
BYTE
9
A3
to data registers, while the WP pin going low after internal
write cycle has started, will have no effect on any write
operation. The CAT5409 will accept both slave addresses
and instructions, but the data registers are protected from
programming by the device’s failure to send an
acknowledge after data is received.
Instruction Byte
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I [3:0].
The R1 and R0 bits point to one of the four data registers of
each associated potentiometer. The least two significant bits
point to one of four Wiper Control Registers. The format is
shown in Figure 9.
Table 11. DATA REGISTER SELECTION
The next byte sent to the CAT5409 contains the
R1
Data Register
A3
A2
A
C
K
Selection
Data Register Selected
DR1 WCRDATA
A1
R0
A0
Slave Address
DR0
DR1
DR2
DR3
A2
A
C
K
P
O
S
T
P
WCR/Pot Selection
P1
A1
(LSB)
(LSB)
A0
P0
R1
0
0
1
1
R0
0
1
0
1