CAT5419WI-25-T1 ON Semiconductor, CAT5419WI-25-T1 Datasheet - Page 7

• Manufacturer Part Number: CAT5419WI-25-T1
• Description: IC POT DPP DUAL 64TAP I2C 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5419WI-25-T1

• Taps: 64
• Resistance (ohms): 25K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 25K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Bus Protocol
protocol:
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5419 will be considered a slave device
in all applications.
START Condition
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT5419 monitors the SDA and
SCL lines and will not respond until this condition is met.
STOP Condition
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
START condition. The Master then sends the address of the
The following defines the features of the 2−wire bus
The device controlling the transfer is a master, typically a
The START Condition precedes all commands to the
A LOW to HIGH transition of SDA when SCL is HIGH
The bus Master begins a transmission by sending a
1. Data transfer may be initiated only when the bus is
2. During a data transfer, the data line must remain
not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
FROM TRANSMITTER
FROM RECEIVER
DATA OUTPUT
DATA OUTPUT
SCL FROM
MASTER
START
Figure 5. Acknowledge Timing
1
http://onsemi.com
7
particular slave device it is requesting. The four most
significant bits of the 8−bit slave address are fixed as 0101
for the CAT5419 (see Figure 5). The next four significant
bits (A3, A2, A1, A0) are the device address bits and define
which device the Master is accessing. Up to sixteen devices
may be individually addressed by the system. Typically,
+5 V and ground are hard−wired to these pins to establish
the device’s address.
address byte, the CAT5419 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
Acknowledge
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5419 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
After the Master sends a START condition and the slave
After a successful data transfer, each receiving device is
The CAT5419 responds with an acknowledge after
When the CAT5419 is in a READ mode it transmits 8 bits
8
ACKNOWLEDGE
9