CAT5419WI-25-T1 ON Semiconductor, CAT5419WI-25-T1 Datasheet - Page 8

• Manufacturer Part Number: CAT5419WI-25-T1
• Description: IC POT DPP DUAL 64TAP I2C 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5419WI-25-T1

• Taps: 64
• Resistance (ohms): 25K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 25K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write Operations
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the requested
operation of CAT5419. The instruction byte consist of a
four−bit opcode followed by two register selection bits and
two pot selection bits. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the selected register. The CAT5419
acknowledges once more and the Master generates the
STOP condition, at which time if a nonvolatile data register
is being selected, the device begins an internal programming
cycle to non−volatile memory. While this internal cycle is in
progress, the device will not respond to any request from the
Master device.
Acknowledge Polling
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation, the
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
In the Write mode, the Master device sends the START
The disabling of the inputs can be used to take advantage
BUS ACTIVITY:
SDA LINE
MASTER
CAT5419
R
S
A
T
T
S
Fixed
0
SLAVE/DPP
ADDRESS
Figure 6. Slave Address Bits
1
Variable
Figure 7. Write Timing
http://onsemi.com
0
A
C
K
1
INSTRUCTION
8
A3
BYTE
CAT5419 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address. If the CAT5419 is
still busy with the write operation, no ACK will be returned.
If the CAT5419 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.
Write Protection
against inadvertent programming of the non−volatile data
registers. If the WP pin is tied to LOW, the data registers are
protected and become read only. Similarly, WP pin going
LOW after Start will interrupt non−volatile write to data
registers, while WP pin going LOW after internal write
cycle has started will have no effect on any write operation.
The CAT5419 will accept both slave addresses and
instructions, but the data registers are protected from
programming by the device’s failure to send an
acknowledge after data is received.
The Write Protection feature allows the user to protect
A2
A1
C
A
K
A0
DR1 WCR DATA
C
A
K
O
S
P
P
T