ADBM-A350-200 Avago Technologies US Inc., ADBM-A350-200 Datasheet - Page 10

• Manufacturer Part Number: ADBM-A350-200
• Description: Vigor Colossus OFN Module
• Manufacturer: Avago Technologies US Inc.

Specifications of ADBM-A350-200

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Video Dump
ADBM-A350 comes with a unique feature that enables
user to capture the image the optical sensor is seeing on
the tracking surface. This is achieved through storing the
pixel data, transferring or dumping the pixels data out to
the host for processing and rebuilding the video dump
image. The rebuilding of video dump image is mainly con-
verting each 8-bit pixel data to form a grayscale digital
image.
Some useful applications for this feature are sensor con-
tamination inspection at manufacturing lines, image rec-
ognition, motion sensing applications and etc.
Fast Video Dump Commands
The host will connect to the OFN sensor and send the
following register commands to initiate video dump. The
following procedure is outlined below.
1. Sensor power up.
2. Read sensor address 0x00 for correct product ID or PID.
3. Write sensor address 0x3a with 0x5a hex.
4. Provide a 24 MHz clock into GPIO pin at VDDIO level.
5. Write sensor address 0x28 with 0x01 hex.
6. Sensor will start to video dump with frame start for
7. Write sensor address 0x3a with 0x5a hex to perform
Figure 4. Output pin status and Frame Start
10
~500 ms.
soft reset or perform a hard reset to reset sensor back
to normal operation.
Fast Video Dump Setup
There are several signals which need to be tapped. They
are namely EVENT_INT, MISO_SDA and GPIO pin of the
sensor. GPIO will be input while MISO_SDA and EVENT_
INT are the output pins that the host controller must
interface to the sensor, readout the data and then build
the video dump image.
Referenced to Figure 10 above, the sensor will output
signals based on the 24 MHz clock signal via the GPIO
pin. Executing the sequence of register setting outlined in
Video Dump Commands above will initiate video dump.
After step #6, each MISO_SDA pin and EVENT_INT pin will
go high for 4 clock cycles. This indicates pixel frame start.
Then after 4 clock cycles, MISO_SDA pin will go low and
EVENT_INT pin is still high. This indicates pixel begin state.
The pixel bits will start to clock thereafter. Each pixel is
represented by an 8-bit data or value. MISO_SDA pin will
output the most signifi cant bits D7 to D4 and Motion pin
will output the least signifi cant bits D3 to D0. Then a pixel
end state (a high in MISO_SDA and low in EVENT_INT) will
follow. This completes the fi rst pixel address 0 data. The
next pixel address 1 data is then clocked out with a pixel
begin state, 4 clock cycles of data followed by a pixel end
state in the same manner. This will continue until all the
361 pixels (19x19 pixel array) data is read.
Pin
GPIO
MISO_SDA
EVENT_INT
Status
Input
Output
Output
Description
24MHz clock signal
Pixel data bits 7 to 4
Pixel data bits 3 to 0