AD5405YCPZ Analog Devices Inc, AD5405YCPZ Datasheet - Page 18

• Manufacturer Part Number: AD5405YCPZ
• Description: IC DAC DUAL 12BIT MULT 40-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD5405YCPZ

• Data Interface: Parallel
• Settling Time: 80ns
• Number Of Bits: 12
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 50µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Resolution (bits): 12bit
• Sampling Rate: 21.3MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analogue: 2.5V To 5.5V
• Supply Current: 500nA
• Digital Ic Case Style: CSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5405EB - BOARD EVAL FOR AD5405
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD5405
PARALLEL INTERFACE
Data is loaded into the AD5405 in a 12-bit parallel word format.
Control lines CS and R/ W allow data to be written to or read
from the DAC register. A write event takes place when CS and
R/ W are brought low, data available on the data lines fills the
shift register, and the rising edge of CS latches the data and
transfers the latched data-word to the DAC register. The DAC
latches are not transparent; therefore, a write sequence must
consist of a falling and rising edge on CS to ensure that data is
loaded into the DAC register and that its analog equivalent is
reflected on the DAC output. A read event takes place when
R/ W is held high and CS is brought low. Data is loaded from the
DAC register, goes back into the input register, and is output
onto the data line, where it can be read back to the controller for
verification or diagnostic purposes. The input and DAC
registers of these devices are not transparent; therefore, a falling
and rising edge of CS is required to load each data-word.
MICROPROCESSOR INTERFACING
ADSP-21xx-to-AD5405 Interface
Figure 38 shows the AD5405 interfaced to the ADSP-21xx
series of DSPs as a memory-mapped device. A single wait state
may be necessary to interface the AD5405 to the ADSP-21xx,
depending on the clock speed of the DSP. The wait state can be
programmed via the data memory wait state control register of
the ADSP-21xx (see the ADSP-21xx family’s user manual for
details).
ADSP-21xx
1
ADDITIONAL PINS OMITTED FOR CLARITY.
DATA 0 TO
ADDR
DATA 23
ADRR
0
DMS
1
TO
WR
13
Figure 38. ADSP21xx-to-AD5405 Interface
DECODER
ADDRESS
ADDRESS BUS
DATA BUS
R/W
DB0 TO DB11
CS
AD5405
1
Rev. B | Page 18 of 24
8xC51-to-AD5405 Interface
Figure 39 shows the interface between the AD5405 and the
8xC51 family of DSPs. To facilitate external data memory
access, the address latch enable (ALE) mode is enabled. The low
byte of the address is latched with this output pulse during
access to the external memory. AD0 to AD7 are the multiplexed
low order addresses and data bus; they require strong internal
pull-ups when emitting 1s. During access to external memory,
A8 to A15 are the high order address bytes. Because these ports
are open drained, they also require strong internal pull-ups
when emitting 1s.
1
ADSP-BF5xx-to-AD5405 Interface
Figure 40 shows a typical interface between the AD5405 and the
ADSP-BF5xx family of DSPs. The asynchronous memory write
cycle of the processor drives the digital inputs of the DAC. The
AMS x line is actually four memory select lines. Internal ADDR
lines are decoded into AMS
chip selects. The rest of the interface is a standard handshaking
operation.
ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-BF5xx
8051
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD0 TO AD7
DATA 0 TO
ADDR
A8 TO A15
1
DATA 23
ADRR
AMSx
1
AWE
ALE
TO
WR
19
1
Figure 40. ADSP-BF5xx-to-AD5405 Interface
Figure 39. 8xC51-to-AD5405 Interface
ADDRESS
DECODER
ADDRESS
DECODER
LATCH
8-BIT
3–0
; these lines are then inserted as
ADDRESS BUS
DATA BUS
ADDRESS BUS
DATA BUS
R/W
DB0 TO DB11
R/W
DB0 TO DB11
CS
CS
AD5405
AD5405
1
1