AD5405YCPZ Analog Devices Inc, AD5405YCPZ Datasheet - Page 5

• Manufacturer Part Number: AD5405YCPZ
• Description: IC DAC DUAL 12BIT MULT 40-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD5405YCPZ

• Data Interface: Parallel
• Settling Time: 80ns
• Number Of Bits: 12
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 50µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Resolution (bits): 12bit
• Sampling Rate: 21.3MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analogue: 2.5V To 5.5V
• Supply Current: 500nA
• Digital Ic Case Style: CSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5405EB - BOARD EVAL FOR AD5405
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
V
Table 2.
Parameter
Write Mode
Data Readback Mode
Update Rate
1
Guaranteed by design and characterization, not subject to production test.
REF
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
14
15
16
17
10
11
12
13
= 10 V, I
1
OUT
2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T
DACA/DACB
LDAC
LDAC
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
DATA
1
2
R/W
CS
Limit at T
0
0
10
10
0
6
0
5
7
10
12
10
10
0
0
5
35
5
10
21.3
MIN
t
1
, T
MAX
OUTPUT
DATA VALID
t
t
PIN
3
6
TO
Figure 3. Load Circuit for Data Timing Specifications
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns max
ns typ
ns max
MSPS
t
4
t
17
t
t
C
50pF
2
5
L
200 μ A
200 μ A
Figure 2. Timing Diagram
t
7
Conditions/Comments
R/W-to-CS setup time
R/W-to-CS hold time
CS low time
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
CS rising-to-LDAC falling time
LDAC pulse width
CS rising-to-LDAC rising time
LDAC falling-to-CS rising time
Address setup time
Address hold time
Data access time
Bus relinquish time
Consists of CS min high time, CS low time, and output voltage settling time
Rev. B | Page 5 of 24
t
9
t
8
DD
I
I
) and timed from a voltage level of (V
OH
OL
t
10
t
12
V
OH (MIN)
DATA VALID
t
+ V
11
2
OL (MAX)
t
14
t
13
t
2
MIN
t
15
t
to T
16
MAX
IL
, unless otherwise noted.
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,
AD5405