AD9785BSVZ Analog Devices Inc, AD9785BSVZ Datasheet - Page 2
![IC DAC 12BIT 800MSPS 100TQFP](/photos/6/60/66082/sv-100-1_sml.jpg)
AD9785BSVZ
Manufacturer Part Number
AD9785BSVZ
Description
IC DAC 12BIT 800MSPS 100TQFP
Manufacturer
Analog Devices Inc
Series
TxDAC®r
Datasheet
1.AD9785BSVZ.pdf
(64 pages)
Specifications of AD9785BSVZ
Data Interface
Serial
Number Of Bits
12
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
450mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Resolution (bits)
12bit
Sampling Rate
800MSPS
Input Channel Type
Parallel
Digital Ic Case Style
QFP
No. Of Pins
100
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Settling Time
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9785BSVZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Company:
Part Number:
AD9785BSVZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
AD9785BSVZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD9785/AD9787/AD9788
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 21
SPI Register Map ............................................................................. 24
Input Data Ports .............................................................................. 33
REVISION HISTORY
2/09—Rev. 0 to Rev. A
Added Settling Time, to Within ±0.5 LSBs Parameter, Table 1 .. 3
Added REFCLK Frequency Range, PLL Enabled Parameter,
Table 2 ................................................................................................ 4
Changes to SPI_SDIO—Serial Data I/O Section ....................... 23
Changes to Table 9 .......................................................................... 24
Changes to Table 11 ........................................................................ 26
Changes to Table 12 ........................................................................ 27
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications .......................................................................... 5
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Serial Port Interface .................................................................... 21
SPI Register Descriptions .......................................................... 25
Single-Port Mode ........................................................................ 33
Dual-Port Mode .......................................................................... 33
Input Data Referenced to DATACLK ...................................... 33
Input Data Referenced to REFCLK .......................................... 35
Optimizing the Data Input Timing .......................................... 36
Rev. A | Page 2 of 64
Digital Datapath ............................................................................. 38
Device Synchronization ................................................................. 42
Driving the REFCLK Input ........................................................... 47
Analog Outputs............................................................................... 50
Power Dissipation ........................................................................... 52
AD9785/AD9787/AD9788 Evaluation Boards........................... 54
Outline Dimensions ....................................................................... 62
Changes to Table 13 ....................................................................... 28
Changes to Table 22 ....................................................................... 32
Changes to Dual-Port Mode Section ........................................... 33
Changes to Input Data RAM Section .......................................... 37
Changes to Digital Amplitude and Offset Control Section ...... 41
Changes to Direct Clocking Section ............................................ 47
1/08—Revision 0: Initial Version
Input Data RAM ......................................................................... 37
Interpolation Filters ................................................................... 38
Quadrature Modulator .............................................................. 40
Numerically Controlled Oscillator .......................................... 40
Inverse Sinc Filter ....................................................................... 40
Digital Amplitude and Offset Control .................................... 41
Digital Phase Correction ........................................................... 41
Synchronization Logic Overview ............................................. 42
Synchronizing Devices to a System Clock .............................. 44
Synchronizing Multiple Devices to Each Other ..................... 45
Interrupt Request Operation .................................................... 46
DAC REFCLK Configuration ................................................... 47
Digital Amplitude Scaling ......................................................... 50
Output Configuration ................................................................ 54
Digital Picture of Evaluation Board ......................................... 54
Evaluation Board Software ........................................................ 55
Evaluation Board Schematics ................................................... 56
Ordering Guide .......................................................................... 62