AD5452YRMZ Analog Devices Inc, AD5452YRMZ Datasheet - Page 20

• Manufacturer Part Number: AD5452YRMZ
• Description: IC DAC 12BIT MULT 50MHZ 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5452YRMZ

• Data Interface: Serial
• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139)
• Settling Time: 110ns
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resolution (bits): 12bit
• Sampling Rate: 2.7MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 2.5V To 5.5V
• Supply Current: 400nA
• Digital Ic Case: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5450/AD5451/AD5452
SERIAL INTERFACE
The AD5450/AD5451/AD5452 have an easy-to-use 3-wire
interface that is compatible with SPI/QSPI/MICROWIRE and
DSP interface standards. Data is written to the device in 16-bit
words. This 16-bit word consists of two control bits and either
8, 10, or 12 data bits, as shown in Figure 46, Figure 47, and
Figure 48. The AD5452 uses 12 bits and ignores the 2 LSBs, the
AD5451 uses 10 bits and ignores the 4 LSBs, and the AD5450
uses 8 bits and ignores the 6 LSBs.
DAC Control Bits C1, C0
Control Bits C1 and C0 allow the user to load and update the
new DAC code and to change the active clock edge. By default,
the shift register clocks data upon the falling edge; this can be
changed via the control bits. If changed, the DAC core is
inoperative until the next data frame. A power cycle resets the
core to default condition. On-chip power-on reset circuitry
ensures that the device powers on with zero scale loaded to the
DAC register and I
Table 10. DAC Control Bits
C1
0
0
1
1
SYNC Function
SYNC is an edge-triggered input that acts as a frame-
synchronization signal and chip enable. Data can only be
transferred to the device while SYNC is low. To start the serial
data transfer, SYNC should be taken low, observing the
minimum SYNC falling to SCLK falling edge setup time, t
minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
upon the falling edge of SYNC . The SCLK and SDIN input
buffers are powered down upon the rising edge of SYNC .
After the falling edge of the 16
to transfer data from the input shift register to the DAC register.
CONTROL BITS
CONTROL BITS
CONTROL BITS
DB15 (MSB)
DB15 (MSB)
DB15 (MSB)
C1
C1
C1
C0
C0
C0
C0
0
1
0
1
DB11 DB10
DB7 DB6 DB5 DB4 DB3 DB2
DB9
Figure 47. AD5451 10-Bit Input Shift Register Contents
Figure 48. AD5452 12-Bit Input Shift Register Contents
Figure 46. AD5450 8-Bit Input Shift Register Contents
DB8
Function Implemented
Load and update(power-on default)
Reserved
Reserved
Clock data to shift register upon rising edge
DB9
DB7 DB6
OUT
DB8
line.
DB7 DB6 DB5 DB4 DB3 DB2
DB5 DB4 DB3 DB2
DATA BITS
DATA BITS
DATA BITS
th
DB1
SCLK pulse, bring SYNC high
DB0
DB1
X
DB0
X
DB1
X
X
DB0
X
X
DB0 (LSB)
DB0 (LSB)
DB0 (LSB)
X
X
X
4
. To
X
X
X
Rev. 0 | Page 20 of 28
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5450/AD5451/AD5452
DAC is through a serial bus that uses standard protocol and is
compatible with microcontrollers and DSP processors. The
communication channel is a 3-wire interface consisting of a
clock signal, a data signal, and a synchronization signal. The
AD5450/AD5451/AD5452 require a 16-bit word, with the
default being data valid upon the falling edge of SCLK, but this
is changeable using the control bits in the data-word.
ADSP-21xx-to-AD5450/AD5451/AD5452 Interface
The ADSP-21xx family of DSPs is easily interfaced to a
AD5450/AD5451/AD5452 DAC without the need for extra glue
logic. Figure 49 is an example of an SPI interface between the
DAC and the ADSP-2191M. SCK of the DSP drives the serial
data line, SDIN. SYNC is driven from one of the port lines, in
this case SPIxSEL.
A serial interface between the DAC and DSP SPORT is shown
in Figure 50. In this example, SPORT0 is used to transfer data to
the DAC shift register. Transmission is initiated by writing a
word to the Tx register after the SPORT has been enabled. In a
write sequence, data is clocked out upon each rising edge of the
DSP’s serial clock and clocked in the DAC input shift register
upon the falling edge of its SCLK. The update of the DAC
output takes place upon the rising edge of the SYNC signal.
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame SYNC delay and frame SYNC setup-and-hold, data delay
and data setup-and-hold, and SCLK width. The DAC interface
expects a t
of 13 ns minimum. See the ADSP-21xx User Manual for infor-
mation on clock and frame SYNC frequencies for the SPORT
register. Table 11 shows the setup for the SPORT control register.
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
ADSP-2101/
ADSP-2103/
ADSP-2191*
ADSP-2191*
Figure 49. ADSP-2191 SPI-to-AD5450/AD5451/AD5452 Interface
Figure 50. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-
4
SPIxSEL
( SYNC falling edge to SCLK falling edge setup time)
SCLK
MOSI
SCK
TFS
DT
AD5450/AD5451/AD5452 Interface
AD5450/AD5451/
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK
AD5450/AD5451/
AD5452*
AD5452*