CYS25G0101DX-ATC Cypress Semiconductor Corp, CYS25G0101DX-ATC Datasheet
CYS25G0101DX-ATC
Specifications of CYS25G0101DX-ATC
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CYS25G0101DX-ATC Summary of contents
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... Cypress Semiconductor Corporation Document Number: 38-02009 Rev. *L SONET OC-48 Transceiver Functional Description The CYS25G0101DX SONET OC-48 Transceiver is a commu- nications building block for high speed SONET data communica- tions. It provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and data recovery operations in a single chip optimized for full SONET compliance ...
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... LOOPA OUT ± Document Number: 38-02009 Rev. *L (155.52 MHz) REFCLK ± TXCLKO TX PLL X16 ÷ Bit-Clock Lock-to-Data/ Clock Control Logic PWRDN LOCKREF SD LFI CYS25G0101DX (155.52 MHz) RXCLK RXD[15:0] 16 Output Register ÷ 16 Shifter Recovered Bit-Clock RX CDR Retimed PLL Data Lock-to-Ref DIAGLOOP IN ± ...
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... Interface Document Number: 38-02009 Rev. *L Multiple loopback and loop through modes are available for both diagnostic and normal operation. For systems containing redundant SONET rings that are maintained in standby, the CYS25G0101DX may also be dynamically powered down to conserve system power. CYS25G0101DX 16 TXD[15:0] ...
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... Pins 113 and 119 are either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 are either no connect or VCCQ. Use VCCQ for compatibility with next generation of OC-48 SERDES devices. Document Number: 38-02009 Rev. *L Top View Top View CYS25G0101DX CYS25G0101DX CYS25G0101DX [ ...
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... The TXCLKI samples the data, TXD [15:0], on the rising edge of the clock cycle. TXCLKO HSTL Clock output Transmit Clock Output. Divide the selected transmit bit rate clock used to coordinate byte wide transfers between upstream logic and the CYS25G0101DX. V Input Analog Reference Voltage for HSTL Parallel Input Bus. V REF ...
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... Table 1. CYS25G0101DX OC-48 SONET Transceiver (continued) Pin Name I/O Characteristics Loop Control Signals DIAGLOOP LVTTL input Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive clock and data recovery then presented at the RXD[15:0] outputs. When LOW, received serial data is routed through the receive clock and data recovery then presented at the RXD[15:0] outputs ...
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... CYS25G0101DX also provides various loopback functions. CYS25G0101DX Transmit Data Path Operating Modes The transmit path of the CYS25G0101DX supports 16-bit wide data paths. Phase Align Buffer Data from the input register is passed to a phase align buffer (FIFO). This buffer is used to absorb clock phase differences between the transmit input clock and the internal character clock ...
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... RESET and FIFO_RST signals should be asserted LOW along with PWRDN signal to ensure low power dissipation. LVPECL Compliance The CYS25G0101DX HSTL parallel I/O can be configured to LVPECL compliance with slight termination modifications. On the transmit side of the transceiver, the TXD[15:0] and TXCLKI are made LVPECL compliant by setting LVPECL signal – ...
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... Low = –3.0V, High = 0 Max Max Max MHz CC Test Conditions [5] Test Conditions Max. IN IEHH Min. IN IELL CYS25G0101DX CC (1.5). Power supply ramping may occur /V relationship is CC DDQ V V DDQ CC [4] 1.4V to 1.6V 3.3V ± 10% [4] 3.3V ± 10% Min Max Unit 2.4 V 0.4 V –20 –90 mA 2.1 V – ...
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... Figure 3. Differential Waveform Definition )-V (-) Test Conditions V = min –4 min 4 OUT V = max DDQ IN DDQ V = max DDQ max MHz DDQ CYS25G0101DX Min Max Unit – 0.5 V – 0. – 1.2 V – 0 560 1600 mV 280 800 mV 25 1000 mV 50 2000 1.2 V Min Max Unit V – ...
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... LVPECL Input Test Waveform Figure 5. AC Test Loads 100Ω 100Ω 100Ω OUT+ ≤ (Includes fixture and OUT– probe capacitance) (b) CML AC Test Load CYS25G0101DX V ICHH 80% 80% 20% V ICLL < 150 ps V IEHH 80% 20% V IELL < 1.0 ns 1.5V R1 OUTPUT C L ...
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... RXCLk rise time and fall times are measured at the percentile region of the rising and falling edge of the clock signal. 7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are shown in 8. +20 ppm is required to meet the SONET output frequency specification. ...
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... Jitter Waveforms Figure 6. Jitter Transfer Waveform of CYS25G0101DX Figure 7. Jitter Tolerance Waveform of CYS25G0101DX Figure 8. CYS25G0101DX Reference Clock Phase Noise Limits Notes 12. The bench jitter measurements are performed using an Agilent Omni bert SONET jitter tester. Document Number: 38-02009 Rev. *L CYS25G0101DX [12] . [12] Page [+] Feedback ...
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... RXD[15:0] RXD[15:0] Typical IO Terminations Limiting Amp 0.1 μ F OUT+ OUT– 0.1 μ S25G0101DX 0.1 μ F OUT+ OUT– 0.1 μ F Note 13. Serial output of CYS25G0101DX is source matched to 50 Document Number: 38-02009 Rev. *L Figure 9. Transmit Interface Timing TXCLKI TXCLKI TXCLKI TXCLKIDL TXCLKIDL ...
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... Zo=50 Ω 82 Ω 0.1uF Figure 17. Clock Oscillator Termination CY S25G0101DX VCC Zo=50 Ω 130 Ω VCC 82 Ω 130 Ω Zo=50 Ω 82 Ω Reference Cloc k Input CYS25G0101DX FRAMER HSTL INPUT FRAMER HSTL INPUT FRAMER LVPECL INPUT Refcloc k Inter nall y Biased Page [+] Feedback ...
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... Speed Ordering Code Standard CYS25G0101DX-AEXC Standard CYS25G0101DX-AEXI Package Diagram Figure 18. 120-Pin Exposed Pad TQFP (14X14X1.0) AE120 (001-48723) Document Number: 38-02009 Rev. *L Package Name Package Type AE120 120-pin Pb-Free TQFP AE120 120-pin Pb-Free TQFP CYS25G0101DX Operating Range Commercial Industrial 001-48723 ** Page [+] Feedback ...
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... Document History Page Document Title: CYS25G0101DX SONET OC-48 Transceiver Document Number: 38-02009 Submission REV. ECN NO. Date ** 105847 03/22/01 *A 108024 06/20/01 *B 111834 12/18/01 *C 112712 02/06/02 *D 113791 04/24/02 *E 115940 05/22/02 *F 117906 09/06/02 *G 119267 10/17/02 *H 121019 11/06/02 *I 122319 12/30/02 *J 124438 02/13/03 *K 1309983 07/27/07 *L 2647349 01/26/09 Document Number: 38-02009 Rev ...
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... All products and company names mentioned in this document may be the trademarks of their respective holders. PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image.cypress.com CAN 2.0b USB Revised January 26, 2009 CYS25G0101DX psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page [+] Feedback ...