CYS25G0101DX-ATC Cypress Semiconductor Corp, CYS25G0101DX-ATC Datasheet - Page 8

• Manufacturer Part Number: CYS25G0101DX-ATC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYS25G0101DX-ATC

• Number Of Transmitters: 1
• Number Of Receivers: 1
• Power Supply Requirement: Single
• Package Type: TQFP
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / Rohs Status: Not Compliant

Deserializer
The CDR circuit extracts bits from the serial data stream and
clocks these bits into the Deserializer at the bit clock rate. The
Deserializer converts serial data into parallel data. RXD[15] is the
most significant bit of the output word and is received first on the
serial interface.
Loopback Timing Modes
CYS25G0101DX supports various loopback modes, as
described in the following sections.
Facility Loopback (Line Loopback with Retiming)
When the LINELOOP signal is set HIGH, the Facility Loopback
mode is activated and the high speed serial receive data (IN±) is
presented to the high speed transmit output (OUT±) after
retiming. In Facility Loopback mode, the high speed receive data
(IN±) is also converted to parallel data and presented to the low
speed receive data output pins (RXD[15:0]). The receive
recovered clock is also divided down and presented to the low
speed clock output (RXCLK).
Equipment Loopback (Diagnostic Loopback with Retiming)
When the DIAGLOOP signal is set HIGH, transmit data is looped
back to the RX PLL, replacing IN±. Data is looped back from the
parallel TX inputs to the parallel RX outputs. The data is looped
back at the internal serial interface and goes through transmit
shifter and the receive CDR. SD is ignored in this mode.
Line Loopback Mode (Non-retimed Data)
When the LOOPA signal is set HIGH, the RX serial data is
directly buffered out to the transmit serial data. The data at the
serial output is not retimed.
Document Number: 38-02009 Rev. *L
Loop Timing Mode
When the LOOPTIME signal is set HIGH, the TX PLL is
bypassed and the receive bit rate clock is used for the transmit
side shifter.
Reset Modes
ALL logic circuits in the device are reset using RESET and
FIFO_RST signals. When RESET is set LOW, all logic circuits
except FIFO are internally reset. When FIFO_RST is set LOW,
the FIFO logic is reset.
Power Down Mode
CYS25G0101DX provides a global power down signal PWRDN.
When LOW, this signal powers down the entire device to a
minimal power dissipation state. RESET and FIFO_RST signals
should be asserted LOW along with PWRDN signal to ensure
low power dissipation.
LVPECL Compliance
The CYS25G0101DX HSTL parallel I/O can be configured to
LVPECL compliance with slight termination modifications. On
the transmit side of the transceiver, the TXD[15:0] and TXCLKI
are made LVPECL compliant by setting V
of a LVPECL signal) to V
signal on the receiver side, set the VDDQ to 3.3V and the trans-
mission lines needs to be terminated with the Thévenin equiv-
alent of Z
series resistor at the driver end of the line to reduce the 3.3V
swing level to a LVPECL swing level (see
This circuit needs to be used on all 16 RXD[15:0] pins, TXCLKO,
and RXCLK. The voltage divider is calculated assuming the
system is built with 50
ο
at LVPECL ref. The signal is then attenuated using a
Ω
transmission lines.
CC
– 1.33V. To emulate an LVPECL
CYS25G0101DX
Figure 14
REF
(reference voltage
Page 8 of 18
on page 15).
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