PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 42

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
If any configuration state affecting memory transaction forwarding is changed by a
configuration write operation on the primary bus at the same time that memory
transactions are ongoing on the secondary bus, response to the secondary bus memory
transactions is not predictable. Configure the memory-mapped I/O base and limit address
registers, prefetchable memory base and limit address registers, and VGA mode bit before
setting the memory enable and master enable bits, and change them subsequently only
when the primary and secondary PCI buses are idle.
4.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses
that cannot automatically be pre-fetched but that can be conditionally pre-fetched based on
command type should be mapped into this space. Read transactions to non-prefetchable
space may exhibit side effects; this space may have non-memory-like behavior. PI7C8150
prefetches in this space only if the memory read line or memory read multiple commands
are used; transactions using the memory read command are limited to a single data transfer.
The memory-mapped I/O base address and memory-mapped I/O limit address registers
define an address range that PI7C8150 uses to determine when to forward memory
commands. PI7C8150 forwards a memory transaction from the primary to the secondary
interface if the transaction address falls within the memory-mapped I/O address range.
PI7C8150 ignores memory transactions initiated on the secondary interface that fall into
this address range. Any transactions that fall outside this address range are ignored on the
primary interface and are forwarded upstream from the secondary interface (provided that
they do not fall into the prefetchable memory range or are not forwarded downstream by
the VGA mechanism).
The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge
Architecture Specification does not provide for 64-bit addressing in the memory-mapped
I/O space. The memory-mapped I/O address range has a granularity and alignment of
1MB. The maximum memory-mapped I/O address range is 4GB.
The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base
address register at configuration offset 20h and by a 16-bit memory-mapped I/O limit
address register at offset 22h. The top 12 bits of each of these registers correspond to bits
[31:20] of the memory address. The low 4 bits are hardwired to 0. The lowest 20 bits of the
memory-mapped I/O base address are assumed to be 0 0000h, which results in a natural
alignment to a 1MB boundary. The lowest 20 bits of the memory-mapped I/O limit address
are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block.
Note: The initial state of the memory-mapped I/O base address register is 0000 0000h. The
initial state of the memory-mapped I/O limit address register is 000F FFFFh. Note that the
initial states of these registers define a memory-mapped I/O range at the bottom 1MB block
of memory. Write these registers with their appropriate values before setting either the
memory enable bit or the master enable bit in the command register in configuration space.
To turn off the memory-mapped I/O address range, write the memory-mapped I/O base
address register with a value greater than that of the memory-mapped I/O limit address
register.
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March 19, 2003 – Revision 1.04