PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 87

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PI7C8150ND

Manufacturer Part Number
PI7C8150ND
Description
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI7C8150ND

Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
85C
Package Type
BGA
Rad Hardened
No
Case
BGA
Dc
04+
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C8150ND
Quantity:
65
Part Number:
PI7C8150ND-33
Manufacturer:
SMD
Quantity:
626
Part Number:
PI7C8150ND-33
Manufacturer:
ALTERA
0
14.1.40
14.1.41
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
P_SERR_L STATUS REGISTER – OFFSET 68h
Bit
1:0
3:2
5:4
7:6
8
9
10
11
12
13
15:14
Bit
16
17
18
19
20
21
22
23
Function
Clock 0 disable
Clock 1 disable
Clock 2 disable
Clock 3 disable
Clock 4 disable
Clock 5 disable
Clock 6 disable
Clock 7 disable
Clock 8 disable
Clock 9 disable
Reserved
Function
Address Parity
Error
Posted Write
Data Parity Error
Posted Write
Non-delivery
Target Abort
during Posted
Write
Master Abort
during Posted
Write
Delayed Write
Non-delivery
Delayed Read –
No Data from
Target
Delayed
Transaction
Master Timeout
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Type
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
Description
If either bit is 0, then S_CLKOUT [0] is enabled.
If both bits are 1, then S_CLKOUT [0] is disabled.
If either bit is 0, then S_CLKOUT [1] is enabled.
If both bits are 1, then S_CLKOUT [1] is disabled.
If either bit is 0, then S_CLKOUT [2] is enabled.
If both bits are 1, then S_CLKOUT [2] is disabled.
If either bit is 0, then S_CLKOUT [3] is enabled.
If both bits are 1, then S_CLKOUT [3] is disabled.
If bit is 0, then S_CLKOUT [4] is enabled.
If bit is 1, then S_CLKOUT [4] is disabled and driven low.
If bit is 0, then S_CLKOUT [5] is enabled.
If bit is 1, then S_CLKOUT [5] is disabled and driven low.
If bit is 0, then S_CLKOUT [6] is enabled.
If bit is 1, then S_CLKOUT [6] is disabled and driven low.
If bit is 0, then S_CLKOUT [7] is enabled.
If bit is 1, then S_CLKOUT [7] is disabled and driven low.
If bit is 0, then S_CLKOUT [8] is enabled.
If bit is 1, then S_CLKOUT [8] is disabled and driven low.
If bit is 0, then S_CLKOUT [9] is enabled.
If bit is 1, then S_CLKOUT [9] is disabled and driven low.
Reserved. Returns 00 when read.
Description
1: Signal P_SERR_L was asserted because an address parity error
was detected on P or S bus.
Reset to 0
1: Signal P_SERR_L was asserted because a posted write data parity
error was detected on the target bus.
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver post memory write data to the target after 2
Reset to 0
1: Signal P_SERR_L was asserted because the bridge received a
target abort when delivering post memory write data.
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge received a
master abort when attempting to deliver post memory write data
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver delayed write data after 2
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
read any data from the target after 2
Reset to 0.
1: Signal P_SERR_L was asserted because a master did not repeat a
read or write transaction before master timeout.
Reset to 0.
77
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
24
attempts.
24
attempts.
24
attempts.
PI7C8150

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