MT46V16M16P-5B:F Micron Technology Inc, MT46V16M16P-5B:F Datasheet - Page 70
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MT46V16M16P-5B:F
Manufacturer Part Number
MT46V16M16P-5B:F
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V16M16P-5BF.pdf
(93 pages)
Specifications of MT46V16M16P-5B:F
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.6V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Supply Current
260mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT46V16M16P-5B:F
Manufacturer:
TI
Quantity:
87
Figure 33:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
Command
Command
Address
Address
Address
READ-to-PRECHARGE
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
Notes:
Bank a,
Bank a,
Bank a,
READ
READ
READ
Col n
Col n
Col n
T0
T0
T0
1. Provided
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
7. An ACTIVE command to the same bank is only allowed if
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
assumed that
CL = 2
t
RAS (MIN) is met, a READ command with auto precharge enabled would cause a
NOP
NOP
NOP
T1
T1
T1
CL = 2.5
t
RAS (MIN) is met.
CL = 3
t
AC,
(a or all)
(a or all)
(a or all)
Bank a,
Bank a,
Bank a,
T2
PRE
PRE
PRE
T2
T2
t
DQSCK, and
68
DO
n
T2n
T2n
DO
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
NOP
T3
NOP
T3
NOP
t
DQSQ.
DO
n
t RP
t RP
t RP
T3n
T3n
T3n
Transitioning Data
256Mb: x4, x8, x16 DDR SDRAM
T4
NOP
T4
T4
NOP
NOP
t
RC (MIN) is met.
T4n
©2003 Micron Technology, Inc. All rights reserved.
Bank a,
Bank a,
Bank a,
T5
T5
T5
Row
ACT
ACT
Row
ACT
Row
Don’t Care
Operations