MT41J512M8THD-15E:D Micron Technology Inc, MT41J512M8THD-15E:D Datasheet
MT41J512M8THD-15E:D
Specifications of MT41J512M8THD-15E:D
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MT41J512M8THD-15E:D Summary of contents
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... IDD specifications, and package dimensions. Refer to Micron’s 2Gb DDR3 SDRAM data sheet for complete specifications. (Specifications for base part number MT41J512M4 correlate to TwinDie manufacturing part number MT41J1G4; specifications for base part num- ber MT41J256M8 correlate to TwinDie manufacturing part number MT41J512M8 ...
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... Meg banks x 2 ranks 8K 32K A[14:0] 8 BA[2:0] 2K A[11, 9:0] Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 4Gb: x4, x8 TwinDie DDR3 SDRAM 512 Meg Meg banks x 2 ranks 8K 32K A[14:0] 8 BA[2:0] 1K A[9:0] ©2008 Micron Technology, Inc. All rights reserved. ...
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... DQS NF, DQ6 DQS# V NF, DQ4 DDQ V RAS CAS# DD CS0# WE# BA0 BA2 RESET# A13 Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 4Gb: x4, x8 TwinDie DDR3 SDRAM Ball Assignments and Descriptions NF, NF/TDQS DM, DM/TDQS V V SSQ DDQ DQ1 DQ3 V SSQ ...
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... NF, DQ6 DQS# V NF, DQ4 DDQ V RAS CAS# DD CS0# WE# BA0 BA2 RESET# A13 Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 4Gb: x4, x8 TwinDie DDR3 SDRAM Ball Assignments and Descriptions NF, NF/TDQS DM, DM/TDQS V V SSQ DDQ DQ1 DQ3 V SSQ SSQ ...
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... Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active power-down (row active in any bank) ...
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... NF – No function: When configured device, these balls are NF. When configured device, these balls are defined as TDQS#, DQ[7:4]. PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 4Gb: x4, x8 TwinDie DDR3 SDRAM Ball Assignments and Descriptions REFCA must be maintained at all times (including self REFDQ . SSQ Micron Technology, Inc ...
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... The differential data strobes (DQS, DQS#) are transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. Read and write accesses to the DDR3 SDRAM are burst oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...
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... Figure 4: Functional Block Diagram (32 Meg Banks x 2 Ranks) CS1# RAS# CKE1 CAS# WE# ODT1 RESET# ZQ1 PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 4Gb: x4, x8 TwinDie DDR3 SDRAM Rank 1 (64 Meg banks) Rank 0 (64 Meg banks) CK CK# A[14:0], BA[2:0] DQS, DQS# DQ[3:0] DM Rank 1 ...
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... The minimum limit requirement is for testing purposes. The leakage current on the V pin should be minimal. 3. MAX operating case temperature. T Figure 5 on page 10). 4. Device functionality is not guaranteed if the DRAM device exceeds the maximum T ing operation. Temperature and Thermal Impedance It is imperative that the DDR3 SDRAM device’s temperature specifications, shown in Table 5 on page 10, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications ...
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... Thermal Characteristics Parameter/Condition Operating case temperature Notes: 1. MAX operating case temperature. T (see Figure 5 thermal solution must be designed to ensure the DRAM device does not exceed the max- imum T 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T operation interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh (ASR), if available, must be enabled ...
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... DD4R DD2P0 = DD5B DD2P0 = CDD6 DD6 DD6 = DD6ET DD6ET = DD7 DD2P0 = 2 × DD2P0 values reflect the combined current of both individual die 4Gb: x4, x8 TwinDie DDR3 SDRAM Electrical Specifications -25/ -187/ Width -25E -187E x4 92 107 x8 117 137 x4 117 132 x8 132 152 x4/ x4/ ...
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... DD4W DD2P0 = DD4R DD2P0 = DD5B DD2P0 = CDD6 DD6 DD6 = DD6ET DD6ET = DD7 DD2P0 = 2 × DD2P0 values reflect the combined current of both individual die 4Gb: x4, x8 TwinDie DDR3 SDRAM Electrical Specifications -187/ -15/ Width -187E -15E Units 102 107 x8 102 107 x4/ x4/ x4/ ...
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... 0.8 TYP 8 13 4Gb: x4, x8 TwinDie DDR3 SDRAM Package Dimensions Solder ball material: 96.5% Sn, 3% Ag, 0.5% Cu Substrate material: plastic laminate Mold compound: epoxy novolac Ball A1 ID 1.35 MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. ...
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... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 4Gb: x4, x8 TwinDie DDR3 SDRAM 0.8 ±0.1 Ball ...