MT45W4MW16BCGB-7013 WT Micron Technology Inc, MT45W4MW16BCGB-7013 WT Datasheet - Page 65
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MT45W4MW16BCGB-7013 WT
Manufacturer Part Number
MT45W4MW16BCGB-7013 WT
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT45W4MW16BCGB-7013_WT.pdf
(69 pages)
Specifications of MT45W4MW16BCGB-7013 WT
Operating Temperature (max)
85C
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
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Figure 52:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
DQ[15:0]
LB#/UB#
A[21:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IL
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
OL
IH
IH
IL
OH
OL
OH
Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
Notes:
READ burst identified
Valid address
t SP
t CSP
(WE# = HIGH)
t SP
t SP
t SP
t CEW
1. Nondefault BCR settings for burst READ followed by asynchronous WE#-controlled WRITE:
2. When transitioning between asynchronous and variable-latency burst operations, CE# must
t HD
t HD
fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during
delay.
go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh
opportunity must be provided every
following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns.
High-Z
t HD
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
t ACLK
t OLZ
t BOE
t KHTL
t CLK
Valid output
65
t HD
t HD
t KOH
t
t HZ
t OHZ
CEM. A refresh opportunity is satisfied by either of the
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Note 2
t CBPH
High-Z
t CEW
t AS
Valid address
t CW
t BW
Don’t Care
t AW
©2005 Micron Technology, Inc. All rights reserved.
t WP
t
WC
Timing Diagrams
Valid input
t DW
t HZ
Undefined
t WR
t WPH
t DH
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