ISP1181BBS,557 NXP Semiconductors, ISP1181BBS,557 Datasheet - Page 20
ISP1181BBS,557
Manufacturer Part Number
ISP1181BBS,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1181BBS557.pdf
(73 pages)
Specifications of ISP1181BBS,557
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Compliant
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ISP1181B_3
Product data sheet
10.4.1.3 Short packet
10.4.2 Isochronous endpoints
Normally, the transfer byte count must be set via a control endpoint before any DMA
transfer takes place. When a short packet has been enabled as EOT indicator
(SHORTP = 1), the transfer size is determined by the presence of a short packet in the
data. This mechanism permits the use of a fully autonomous data transfer protocol.
When reading from an OUT endpoint, reception of a short packet at an OUT token will
stop the DMA operation after transferring the data bytes of this packet.
Table 10.
[1]
A DMA transfer to/from an isochronous endpoint can be terminated by any of the following
conditions (bit names refer to the DMA Configuration Register, see
Table 11.
EOT condition
EOT input
DMA Counter Register
Short packet
DMAEN bit in DMA
Configuration Register
EOT condition
EOT input active
DMA Counter Register zero
End-Of-Packet
•
•
•
•
The DMA transfer stops. However, no interrupt is generated.
An external End-Of-Transfer signal occurs on input EOT
The DMA transfer completes as programmed in the DMA Counter register
(CNTREN = 1)
An End-Of-Packet (EOP) signal is detected
DMA operation is disabled by clearing bit DMAEN.
Summary of EOT conditions for a bulk endpoint
Recommended EOT usage for isochronous endpoints
Rev. 03 — 23 January 2009
OUT endpoint
EOT is active
transfer completes as
programmed in the DMA
Counter register
short packet is received and
transferred
DMAEN = 0
OUT endpoint
do not use
do not use
preferred
[1]
Full-speed USB peripheral controller
IN endpoint
EOT is active
transfer completes as
programmed in the DMA
Counter register
counter reaches zero in the
middle of the buffer
DMAEN = 0
IN endpoint
preferred
preferred
do not use
© ST-NXP Wireless 2009. All rights reserved.
Table
ISP1181B
[1]
24):
19 of 72
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