CY8C5246AXI-054 Cypress Semiconductor Corp, CY8C5246AXI-054 Datasheet - Page 10

• Manufacturer Part Number: CY8C5246AXI-054
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-054

• Lead Free Status / Rohs Status: Compliant

Vdda. Supply for all analog peripherals and analog core
regulator. Vdda must be the highest voltage present on the
device. All other supply pins must be less than or equal to
Vdda.
Vddd. Supply for all digital peripherals and digital core regulator.
Vddd must be less than or equal to Vdda.
Vssa. Ground for all analog peripherals.
Vssb. Ground connection for boost pump.
Vssd. Ground for all digital logic and I/O pins.
Vddio0, Vddio1, Vddio2, Vddio3. Supply for I/O pins. Each
Vddio must be tied to a valid operating voltage (1.71 V to 5.5 V),
and must be less than or equal to V
The Cortex-M3 CPU subsystem includes these features:
Document Number: 001-55034 Rev. *F
ARM Cortex-M3 CPU
Programmable Nested Vectored Interrupt Controller (NVIC),
tightly integrated with the CPU core
Full featured debug and trace modules, tightly integrated with
the CPU core
SRAM
SRAM
32 KB
32 KB
Interrupt Inputs
JTAG/SWD
Bus
Matrix
Bus
Matrix
Debug Block
AHB Spokes
(Serial and
Controller
Vectored
Interrupt
Nested
(NVIC)
JTAG)
GPIO &
EMIF
DDA
. If the I/O pins associated
AHB
I- Bus
AHB Bridge & Bus Matrix
Figure 4-1. ARM Cortex-M3 Block Diagram
PRELIMINARY
C-Bus
D-Bus
AHB
Digital
Prog.
Cortex M3 CPU Core
Peripherals
PHUB
AHB
S-Bus
Cortex M3 Wrapper
Analog
Prog.
with Vddio0, Vddio2 or Vddio3 are not used then that Vddio
should be tied to ground (Vssd or Vssa).
XRES (and configurable XRES). External reset pin. Active low
with internal pullup.
4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C52 family of devices has an ARM Cortex-M3 CPU
core. The Cortex-M3 is a low power 32-bit three-stage pipelined
Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is
intended for deeply embedded applications that require fast
interrupt handling features.
Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB
of SRAM
Cache controller
Peripheral HUB (PHUB)
DMA controller
PSoC
DMA
Bus
Matrix
Functions
®
Special
Watchpoint and
Instrumentation
and Breakpoint
5: CY8C52 Family Data Sheet
Trace Module
Trace (DWT)
Flash Patch
(FPB)
(ITM)
Data
Cache
Trace Module
Interface Unit
Embedded
Trace Port
(TPIU)
(ETM)
256 KB
Flash
ECC
Trace Pins:
5 for TRACEPORT or
1 for SWV mode
Page 10 of 88
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