GD82551ER S L66X Intel, GD82551ER S L66X Datasheet - Page 34
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GD82551ER S L66X
Manufacturer Part Number
GD82551ER S L66X
Description
Manufacturer
Intel
Datasheet
1.GD82551ER_S_L66X.pdf
(104 pages)
Specifications of GD82551ER S L66X
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Package Type
BGA
Mounting
Surface Mount
Pin Count
196
Lead Free Status / Rohs Status
Not Compliant
82551ER — Networking Silicon
5.3.1.2
5.3.1.3
5.3.1.4
26
1. For a topology of two 82551ER devices connected by a crossed twisted-pair Ethernet cable, the deep power-down mode should be
disabled. If it is enabled, the two devices may not detect each other if the operating system places them into a low power state before both
nodes become active.
In the D0a state, the 82551ER provides its full functionality and consumes nominal power. In
addition, the 82551ER supports wake on link status change
While it is active, the 82551ER requires a nominal PCI clock signal (in other words, a clock
frequency greater than 16 MHz) for proper operation. During idle time, the 82551ER supports a
PCI clock signal suspension using the Clockrun signal mechanism. The 82551ER supports a
dynamic standby mode. In this mode, the 82551ER is able to save almost as much power as it does
in the static power-down states. The transition to or from standby is done dynamically by the
82551ER and is transparent to the software.
D1 Power State
For a device to meet the D1 power state requirements, as specified in the Advanced Configuration
and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus transmission or
interrupts; however, bus reception is allowed. Therefore, device context may be lost and the
82551ER does not initiate any PCI activity. In this state, the 82551ER responds only to PCI
accesses to its configuration space and system wake-up events.
The 82551ER retains link integrity and monitors the link for any wake-up events such as wake-up
packets or link status change. Following a wake-up event, the 82551ER asserts the PME# signal to
alert the PCI system.
D2 Power State
The ACPI D2 power state is similar in functionality to the D1 power state. If the bus is in the B2
bus power state, the 82551ER will consume less current than it does in the D1 state. In addition to
D1 functionality, the 82551ER can provide a lower power mode with wake-on-link status change
capability. The 82551ER may enter this mode if the link is down while the 82551ER is in the D2
state. In this state, the 82551ER monitors the link for a transition from an invalid link to a valid
link. The 82551ER will not attempt to keep the link alive by transmitting idle symbols or link
integrity pulses.
configuration bit in the Power Management Driver Register (PMDR).
D3 Power State
In the D3 power state, the 82551ER has the same capabilities and consumes the same amount of
power as it does in the D2 state. However, it enables the PCI system to be in the Bus Power 3 (B3)
state. If the PCI system is in the B3 state (in other words, no PCI power is present), the 82551ER
provides wake-up capabilities if it is connected to an auxiliary power source in the system. If
PME# is disabled, the 82551ER does not provide wake-up capability or maintain link integrity. In
this mode, the 82551ER consumes minimal power.
The 82551ER enables a system to be in a sub-5 watt state (low power state) and still be virtually
connected. More specifically, the 82551ER supports full wake-up capabilities while it is in the D3
cold state. The 82551ER can be connected to an auxiliary power source (V
to provide wake-up functionality while the PCI power is off. The typical current consumption of
the 82551ER is 125 mA at 3.3 V and a dual power plane is not required. If connected to an
auxiliary power source, the 82551ER receives all of its power from the auxiliary source in all
power states. When connected to an auxiliary power supply, the 82551ER must have a status
indicator of whether the power supply is valid (in other words, auxiliary power is stable). The
indication is received at the AUXPWR pin, as described next.
1
The sub-10 mA state due to an invalid link can be enabled or disabled by a
(Section 5.3.2, “Wake-up
AUX
), which enables it
Events”).
Datasheet