GD82551ER S L66X Intel, GD82551ER S L66X Datasheet - Page 45
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GD82551ER S L66X
Manufacturer Part Number
GD82551ER S L66X
Description
Manufacturer
Intel
Datasheet
1.GD82551ER_S_L66X.pdf
(104 pages)
Specifications of GD82551ER S L66X
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Package Type
BGA
Mounting
Surface Mount
Pin Count
196
Lead Free Status / Rohs Status
Not Compliant
6.2.4
6.3
6.3.1
6.3.2
Datasheet
10BASE-T Link Integrity and Full Duplex
The link integrity in 10 Mbps works with link pulses. The PHY unit senses and differentiates those
link pulses from fast link pulses and from 100BASE-TX idles. The link beat pulse is also used to
determine if the receive pair polarity is reversed. If it is, the polarity is corrected internally.
The PHY unit supports 10 Mbps full duplex by disabling the collision function, the squelch test,
and the carrier sense transmit function. This allows the PHY unit to transmit and receive
simultaneously, achieving up to 20 Mbps network bandwidth using Auto-Negotiation. Full duplex
can only be used in point-to-point connections (no shared media).
Auto-Negotiation
The PHY unit supports Auto-Negotiation, which is an automatic configuration scheme designed to
manage interoperability in multifunctional LAN environments. An Auto-Negotiation capable
device can detect and automatically configure its port to take maximum advantage of common
modes of operation without user intervention or prior knowledge by either station. Auto-
Negotiation is described in IEEE Standard 802.3u, clause 28.
Description
A PHY’s capability is encoded by bursts of link pulses called Fast Link Pulses (FLPs). Connection
is established by FLP exchange and handshake during link initialization time. After the link is
established by this handshake, the native link pulse scheme resumes. A reset or management re-
negotiate command (through the MDI interface) will restart the process. If the PHY unit cannot
perform Auto-Negotiation, it will set this bit to 0 and determine the speed using Parallel Detection.
The PHY unit supports four technologies: 100BASE-Tx Full and Half Duplex and 10BASE-T Full
and Half Duplex. Since only one technology can be used at a time (after every re-negotiate
command), a prioritization scheme is used to ensure that the ability of the highest common
denominator is chosen.
Parallel Detect and Auto-Negotiation
The PHY unit can automatically determine the speed of the link by using Parallel Detect as an
alternative to Auto-Negotiation. Upon a reset, a link status fail, or a negotiate/re-negotiate
command, the PHY unit inserts a long delay during which no link pulses are transmitted. This
period insures that the PHY unit‘s link partner has gone into a Link Fail state before Auto-
Negotiation or Parallel Detection begins. The PHY unit will look for both FLPs and link integrity
pulses. The following diagram illustrates this process.
Networking Silicon — 82551ER
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