5962-8960101B2A QP SEMICONDUCTOR, 5962-8960101B2A Datasheet - Page 13

• Manufacturer Part Number: 5962-8960101B2A
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-8960101B2A

• Logic Family: ACT
• Technology: CMOS
• Number Of Bits: 8
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Non-Inverting
• Operating Supply Voltage (typ): 5V
• Propagation Delay Time: 13.5ns
• Output Type: 3-State
• Low Level Output Current: 24mA
• High Level Output Current: -24mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
10/ Three-state output conditions are required.
11/ Power dissipation capacitance (C
12/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at
13/ The maximum limit for this parameter at 100 krads (si) is 2.0 µA.
14/ This test is for qualification only. Ground bounce tests are performed on a nonswitching (quiescent) output and are used to
15/ When used in synchronous TTL compatible systems, ground bounce (V
16/ See EIA/JEDEC Standard No. 78 for electrically induced latch-up test methods and procedures. The values listed for I
17/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
18/ Device classes B, S, Q, and V are tested at V
19/ AC limits at V
5/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and
6/ For device classes B, S, Q, and V, this test is guaranteed, if not tested, to the limits specified in table I.
7/ RHA samples do not have to be tested at -55°C and +125°C prior to irradiation.
8/ When performing post irradiation electrical measurements for RHA level, T
9/ Transmission driving tests are performed at V
the direction of current flow respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum
and maximum limits, as applicable, listed herein.
at T
V
x V
I
signal.
V
using the alternate test method, the maximum limits are equal to the number of inputs at a high TTL input level times the
∆I
measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is performed on a low
noise bench test fixture with all outputs fully dc loaded (I
load capacitance (see figure 5). The loads must be located as close as possible to the device output. Inputs are then
conditioned with 1 MHz pulse (t
and all others (possible) are switched. The low level ground bounce noise is measured at the quiet output using a F.E.T.
oscilloscope probe with at least 1 MΩ impedance. Measurement is taken from the peak of the largest positive pulse with
respect to the nominal low level output voltage (figure 5). The device inputs are then conditioned such that the output under
test is at a high nominal V
the largest negative peak. This procedure is repeated such that all outputs are tested at a high and low level with a
maximum number of outputs switching.
and V
patterns used for fault detection. Functional tests shall be performed in sequence as approved by the qualifying activity on
qualified devices. H ≥ 2.5 V, L < 2.5 V; high inputs = 2.4 V and low inputs = 0.4 V. The input voltage levels have the
allowable tolerances in accordance with MIL-STD-883 already incorporated. Functional tests at V
for RHA specified devices.
for screening. Other voltages of V
V
tests, all paths must be tested.
S
IN
IN
CC
, n is the number of device inputs at TTL levels, f is the frequency of the input signal, and d is the duty cycle of the input
CC
CC
= V
= V
A
= 5.5 V are 1.0 ns and guaranteed by guardbanding the V
maximum limit and the preferred method and limits are guaranteed.
DEFENSE SUPPLY CENTER COLUMBUS
) + (n x d x ∆I
= +25°C ±5°C.
over
CC
CC
are to be accurate within ±5 percent.
MICROCIRCUIT DRAWING
or GND. When V
- 2.1 V (alternate method). Classes B, S, Q, and V shall use the preferred method. When the test is performed
COLUMBUS, OHIO 43216-5000
CC
= 5.5 V are equal to the limits at V
CC
STANDARD
x V
CC
OH
) and the dynamic current consumption, I
IN
level. The high level ground bounce measurement is then measured from nominal V
= V
TABLE I. Electrical performance characteristics - Continued.
r
= t
CC
PD
CC
f
) determines the no load dynamic power consumption, P
or GND is used, the test is guaranteed for V
= 3.5 ±1.5 ns) switching simultaneously and in phase such that one output is forced low
and temperatures are guaranteed, if not tested. See 4.4.1d.
CC
CC
= 5.5 V dc with a 2 ms duration maximum. This test may be performed using
= 4.5 V at T
CC
= 4.5 V and guaranteed by testing at V
OL
maximum and I
C
= +125°C for sample testing and at V
CC
= 4.5 V minimum limits to 1.5 ns. For propagation delay
SIZE
S
A
= (C
GBL
PD
OH
A
and V
= +25°C. Limits shown are guaranteed
+ C
minimum = ±24 mA for example) and 50pF of
REVISION LEVEL
IN
L
GBH
)V
= 2.0 V or 0.8 V.
CC
) = 2,000 mV can be a possible problem.
f + I
CC
E
D
CC
+ n x d x ∆I
= (C
= 4.5 V. Minimum ac limits for
CC
PD
CC
= 4.5 V are worst case
+ C
= 4.5 V at T
CC
L
) (V
. For both P
SHEET
5962-89601
CC
x V
OH
C
13
CC
= +25°C
level to
)f + (I
D
trigger
and
CC