CY7C53150-20AI Cypress Semiconductor Corp, CY7C53150-20AI Datasheet - Page 5

• Manufacturer Part Number: CY7C53150-20AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C53150-20AI

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-10001 Rev. *D
downloaded and updated over the LonTalk network from an
external network management tool.
For the CY7C53150, the user application program is stored in
on-chip Flash Memory and also in off-chip memory. The user
program may initially be programmed into the off-chip memory
device using a device programmer.
Flash Memory Retention and Endurance
Data and code stored in Flash Memory is guaranteed to be
retained for at least 10 years for programming temperature
range of –25°C to 85°C.
The Flash Memory can typically be written 100,000 times
without any data loss.
system firmware extends the effective endurance of Flash
memory in two ways. If the data being written to a byte of Flash
memory is the same as the data already present in that byte,
the firmware does not perform the physical write. So for
example, an application that sets its own address in Flash
memory after every reset will not use up any write cycles if the
address has not changed. In addition, system firmware
version 13.1 or higher is able to aggregate writes to eight
successive address locations into a single write for
CY7C53120E4 devices. For example, if 4 KB of code is
downloaded over the network, the firmware would execute
only 512 writes rather than 4,096.
40-MHz 3120 Operation
The CY7C53120E4-40 device was designed to run at
frequencies up to 40 MHz using an external clock oscillator. It
is important to note that external oscillators may typically take
on the order of 5 ms to stabilize after power-up. The Neuron
chip should be held in reset until the CLK1 input is stable. With
some oscillators, this may require the use of a reset-stretching
Low-Voltage Detection chip/circuit. Check the oscillator
vendor’s specification for more information about start-up
stabilization times.
Low-Voltage Inhibit Operation
The on-chip Low-voltage Inhibit circuit trips the Neuron chip
whenever the V
prevents the corruption of nonvolatile memory during voltage
drops.
Communications Port
The Neuron chip includes a versatile 5-pin communications
port that can be configured in three different ways. In
Single-Ended Mode, pin CP0 is used for receiving serial data,
pin CP1 for transmitting serial data, and pin CP2 enables an
external transceiver. Data is communicated using Differential
Manchester encoding.
In Special Purpose Mode, pin CP0 is used for receiving serial
data, pin CP1 for transmitting serial data, pin CP2 transmits a
bit clock, and pin CP4 transmits a frame clock for use by an
external intelligent transceiver. In this mode, the external
Notes:
10. t
5.
6.
7.
8.
9.
For detailed information about data retention after 100K cycles, please see Cypress qualification report.
Hysteresis values are on the condition that the input signal swing is 200 mV greater than the programmed value.
Must be disabled if data rate is 1.25 Mbps or greater.
Receiver input, V
CP0 and CP1 inputs each 0.60 Vp – p, 1.25 MHz sine wave 180° out of phase with each other as shown in Figure 8. V
PLH
: Time from input switching states from low to high to output switching states. t
DD
D
= V
input is less than 4.1 ± 0.3V. This feature
[5]
CP0
An erase/write cycle takes 20 ms. The
– V
CP1
, at least 200 mV greater than hysteresis levels. See Figure 1.
transceiver is responsible for encoding and decoding the data
stream.
In Differential Mode, pins CP0 and CP1 form a differential
receiver with built-in programmable hysteresis and low-pass
filtering. Pins CP2 and CP3 form a differential driver. Serial
data is communicated using Differential Manchester encoding.
The following tables describe the communications port when
used in Differential Mode.
Programmable Hysteresis Values
(Expressed as differential peak-to-peak voltages in terms of V
Programmable Glitch Filter Values
(Receiver (end-to-end) filter values expressed as transient
pulse suppression times)
Receiver
(Worst case across hysteresis)
Differential Receiver (End-to-End) Absolute Symmetry
PHL
Hysteresis
Filter (F)
Filter (F)
: Time from input switching states from high to low to output switching states.
Filter (F)
0
0
1
2
3
0
1
2
3
4
5
6
7
V
0
1
2
3
[8]
CP0
DD
CP1
V
Figure 1. Receiver Input Waveform
(End-to-End) Absolute Asymmetry
/2
CP0 – CP1
hys
[6]
Hysteresis (H)
+ 200 mV
Min.
120
240
480
0.019 V
0.040 V
0.061 V
0.081 V
0.101 V
0.121 V
0.142 V
0.162 V
10
V
hys
0
Min.
Max ( t
DD
DD
DD
DD
DD
DD
DD
DD
DD
1500
Typ.
410
800
75
3 ns
= 5.00 V ± 5%.
PLH
150
250
400
Max ( t
0.027 V
0.054 V
0.081 V
0.108 V
0.135 V
0.162 V
0.189 V
0.216 V
35
V
hys
[7]
– t
Typ.
PHL
CY7C53150
CY7C53120
DD
DD
DD
DD
DD
DD
DD
DD
PLH
24
Max.
1350
2600
140
700
)
– t
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PHL
0.035 V
0.068 V
0.101 V
0.135 V
0.169 V
0.203 V
0.236 V
0.270 V
V
hys
) Unit
Max.
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
[9, 10]
DD
DD
DD
DD
DD
DD
DD
DD
ns
DD
)