EWIXP465BAE Intel, EWIXP465BAE Datasheet - Page 140
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
EWIXP465BAE
Manufacturer Part Number
EWIXP465BAE
Description
Manufacturer
Intel
Datasheet
1.EWIXP465BAE.pdf
(163 pages)
Specifications of EWIXP465BAE
Core Operating Frequency
667MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EWIXP465BAE
Manufacturer:
PANASONIC
Quantity:
240
Company:
Part Number:
EWIXP465BAE
Manufacturer:
INTEL
Quantity:
220
Company:
Part Number:
EWIXP465BAET
Manufacturer:
ATMEL
Quantity:
1 000
Electrical Specifications
5.6.2.7
5.6.2.7.1
Figure 32.
Table 65.
May 2005
140
NOTES:
1. Timing was designed for a system load between 5pF and 60pF for low drive setting at typically no more than a 33MHz clock
2. Timing was designed for a system load between 5pF and 50pF for medium drive setting at typically no more than a 66MHz
3. Timing was designed for a system load between 5pF and 40pF for high drive setting at typically no more than a 80MHz clock
4. Drive settings do not apply to EX_CS_N signals and are expected to be point to point. The timing on this signal was designed
5. EX_control_signals output signals consist of EX_ALE, EX_ADDR, EX_CS_N, EX_GNT_REQ_N, EX_GNT_N, EX_RD_N,
6. EX_control_signals input signals consist of EX_ADDR, EX_CS_N, EX_SLAVE_CS_N, EX_REQ_GNT_N, EX_REQ_N,
Symbol
clock
for a system load between 5pF and 10pF
EX_WR_N, EX_WAIT_N
EX_BURST, EX_RD_N, EX_WR_N
T
T
T
T
T
T
1
2
3
4
5
6
Valid rising edge of EX_CLK to valid signal on the
output.
Valid signal hold time after the rising edge of EX_CLK
Valid data signal on an input prior to the rising edge of
EX_CLK
Required hold time of a data input after the rising edge
of EX_CLK
Valid control/arbiter signal on an input prior to the
rising edge of EX_CLK
Required hold time of a control/arbiter input after the
rising edge of EX_CLK
Expansion Bus
Expansion Bus Synchronous Operation
Expansion Bus Synchronous Timing
Expansion Bus Synchronous Operation Timing Values
EX_DATA, _BE_N, PARITY -
EX_DATA, _BE_N, PARITY -
EX_ control signals -
EX_ control signals -
Parameter
output_signals
input_signals
output_signals
input_signals
EX_CLK
Intel
®
IXP45X and Intel
Min.
0.5
3.5
0.5
Low Drive
1
2
®
IXP46X Product Line of Network Processors Datasheet
Max.
10
T
T
3
5
Min.
0.5
3.5
0.5
Med Drive
1
2
T
T
4
6
T
2
Max.
T
8.5
1
Document Number:
Min.
0.5
3.5
0.5
1
2
Hi Drive
Max.
6.5
Units Notes
ns
ns
ns
ns
ns
ns
306261-002
1, 2, 3,
4
1, 2, 3,
4
1, 2, 3,
4
1, 2, 3,
4
1, 2, 3,
4
1, 2, 3,
4