EWIXP465BAE Intel, EWIXP465BAE Datasheet - Page 48
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EWIXP465BAE
Manufacturer Part Number
EWIXP465BAE
Description
Manufacturer
Intel
Datasheet
1.EWIXP465BAE.pdf
(163 pages)
Specifications of EWIXP465BAE
Core Operating Frequency
667MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EWIXP465BAE
Manufacturer:
PANASONIC
Quantity:
240
Company:
Part Number:
EWIXP465BAE
Manufacturer:
INTEL
Quantity:
220
Company:
Part Number:
EWIXP465BAET
Manufacturer:
ATMEL
Quantity:
1 000
Package Information
Table 11.
May 2005
48
DDRI_CK[2:0]
DDRI_CK_N[2:0]
DDRI_CS_N[1:0]
DDRI_RAS_N
DDRI_CAS_N
DDRI_WE_N
DDRI_DM[4:0]
DDRI_BA[1:0]
DDRI_MA[13:0]
DDRI_DQ[31:0]
DDRI_CB[7:0]
DDRI_DQS[4:0]
NOTE: This table discusses all features supported on the Intel
† For a legend of the Type codes, see
processor, see
Name
DDR SDRAM Interface (Sheet 1 of 2)
Table 1 on page
Power
Reset
on
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
†
Reset
VB
VB
VB
Table 10 on page
14.
Z
Z
Z
Z
Z
Z
Z
0
1
†
Software
Enables
Normal
Reset
After
Until
VO
VO
VO
VO
VO
VO
VO
VO
VO
VB
VB
VB
46.
Software
Enables
Normal
®
After
VO
VO
VO
VO
VO
VO
VO
VO
VO
VB
VB
VB
IXP45X and Intel
Type
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
†
®
DDR SDRAM Clock Out — Provide the positive differential clocks to the external SDRAM
memory subsystem.
DDR SDRAM Clock Out — Provide the negative differential clocks to the external SDRAM
memory subsystem.
Chip Select — Must be asserted for all transactions to the DDR SDRAM device. One per bank.
Row Address Strobe — Indicates that the current address on DDRI_MA[13:0] is the row.
Column Address Strobe — Indicates that the current address on DDRI_MA[13:0] is the
column.
Write Strobe — Defines whether or not the current operation by the DDR SDRAM is to be a
read or a write.
Data Bus Mask — Controls the DDR SDRAM data input buffers. Asserting DDRI_WE_N
causes the data on DDRI_DQ[31:0] and DDRI_CB[7:0] to be written into the DDR SDRAM
devices. DDRI_DM[4:0] controls this operation on a per byte basis. DDRI_DM[3:0] are
intended to correspond to each byte of a word of data. DDRI_DM[4] is intended to be utilized
for the ECC byte of data.
DDR SDRAM Bank Selects — Controls which of the internal DDR SDRAM banks to read or
write. DDRI_BA[1:0] are used for all technology types supported.
Address bits 13 through 0 — Indicates the row or column to access depending on the state of
DDRI_RAS_N and DDRI_CAS_N.
Data Bus — 32-bit wide data bus.
ECC Bus — Eight-bit error correction code which accompanies the data on DDRI_DQ[31:0].
When ECC is disabled and not being used in a system design, these signals are not required
for any connection.
Data Strobes Differential — Strobes that accompany the data to be read or written from the
DDR SDRAM devices. Data is sampled on the negative and positive edges of these strobes.
DDRI_DQS[3:0] are intended to correspond to each byte of a word of data. DDRI_DQS4] is
intended to be utilized for the ECC byte of data.
IXP46X Product Line of Network Processors. For details on feature support listed by
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Datasheet
Description
Document Number:
306261-002