GCIXP1250BA 837411 Intel, GCIXP1250BA 837411 Datasheet - Page 38

• Manufacturer Part Number: GCIXP1250BA 837411
• Manufacturer: Intel

Specifications of GCIXP1250BA 837411

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
3.3.7
38
Table 18. PCI Interface Pins
®
IXP1250 Network Processor
PCI Interface Pins
AD[31:0]
CBE_L[3:0]
PAR
FRAME_L
IRDY_L
TRDY_L
Signal Names
PCI Interface
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[10]
[11]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
D19
C19
B19
D18
C18
B18
A18
E17
B17
A17
B15
C15
D15
E15
A14
B14
C12
D12
E12
B11
C11
D11
A10
C10
A9
E10
B9
C9
D9
A8
E9
B8
D17
C14
B12
D10
A12
E14
A13
D14
Number
Pin
I2/O2/
TS
I2/O2/
TS
I2/O2/
TS
I2/O2/
STS
I2/O2/
STS
I2/O2/
STS
Type
32
4
1
1
1
1
Total
Address/data. These signals are multiplexed address and
data bus. The IXP1250 receives addresses as target and
drives addresses as master. It receives write data and drives
read data as target. It drives write data and receives read
data as master.
Command byte enables. These signals are multiplexed
command and byte enable signals. The IXP1250 receives
commands as target and drives commands as master. It
receives byte enables as target and drives byte enables as
master.
Parity. This signal carries even parity for AD and CBE_L
pins. It has the same receive and drive characteristics as the
address and data bus, except that it occurs on the next PCI
clock cycle.
FRAME_L indicates the beginning and duration of an
access. The IXP1250 receives as target and drives as
master.
Initiator ready. Indicates the master’s ability to complete the
current data phase of the transaction. The IXP1250 receives
as target and drives as master.
Target ready. Indicates the target’s ability to complete the
current data phase of the transaction. The IXP1250 drives as
target and receives as master.
Pin Descriptions
Datasheet