IXP2400 Intel, IXP2400 Datasheet - Page 13
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IXP2400
Manufacturer Part Number
IXP2400
Description
Manufacturer
Intel
Datasheet
1.IXP2400.pdf
(126 pages)
Specifications of IXP2400
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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2.2.4
2.2.5
2.3
Datasheet
Memory Management
The Intel XScale core implements the Memory Management Unit (MMU) Architecture specified
in the ARM Architecture Reference Manual. The MMU provides access protection and virtual to
physical address translation. The MMU Architecture also specifies the caching policies for the
instruction cache and data memory. These policies are specified as page attributes and include:
Branch Target Buffer
The Intel XScale core provides a Branch Target Buffer (BTB) to predict the outcome of
branch-type instructions. It provides storage for the target address of branch-type instructions and
predicts the next address to present to the instruction cache when the current instruction address is
that of a branch. The BTB holds 128 entries.
Microengines
The Microengines (MEs) do most of the programmable per-packet processing in the IXP2400.
There are eight MEs, connected as shown in
(SRAM, DRAM, MSF, etc.) as well as private connections between adjacent MEs.
The MEs provide support for software-controlled multi-threaded operation. Given the disparity in
processor cycle times versus external memory times, a single thread of execution will often block,
waiting for external memory operations to complete. Having multiple threads available allows for
threads to interleave operation; there is often at least one thread ready to run while others are
blocked.
•
•
•
•
•
Identifying code as cacheable or non-cacheable
Selecting between the mini-data cache or data cache
Write-back or write-through data caching
Enabling data write allocation policy
Enabling the write buffer to coalesce stores to external memory
Figure
4. The MEs have access to all shared resources
Intel
®
IXP2400 Network Processor
13
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