EWIXP425BDT Intel, EWIXP425BDT Datasheet - Page 42
EWIXP425BDT
Manufacturer Part Number
EWIXP425BDT
Description
Manufacturer
Intel
Datasheet
1.EWIXP425BDT.pdf
(130 pages)
Specifications of EWIXP425BDT
Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
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Table 12.
Intel
Datasheet
42
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
UTOPIA Level 2 Interface (Sheet 1 of 2)
UTP_OP_CLK
UTP_OP_FCO
UTP_OP_SOC
UTP_OP_DATA[7:0]
UTP_OP_ADDR[4:0]
UTP_OP_FCI
UTP_IP_CLK
†
††
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Power
or Sys
Reset
Reset
Z
Z
Z
Z
Z
Z
Z
Reset
Post
VI
VI
VI
VI
Z
Z
Z
Intel
Type
®
I/O
IXP42X product line and IXC1100 control plane processors
O
O
O
Table 5 on page
I
I
I
†
UTOPIA Transmit clock input. Also known as UTP_TX_CLK.
This signal is used to synchronize all UTOPIA-transmit
outputs to the rising edge of the UTP_OP_CLK.
This signal should be pulled high
resistor when not being utilized in the system.
UTOPIA flow control output signal. Also known as the
TXENB_N signal.
Used to inform the selected PHY that data is being
transmitted to the PHY. Placing the PHY’s address on the
UTP_OP_ADDR — and bringing UTP_OP_FCO to logic 1,
during the current clock — followed by the UTP_OP_FCO
going to a logic 0, on the next clock cycle, selects which
PHY is active in MPHY mode.
In SPHY configurations, UTP_OP_FCO is used to inform
the PHY that the processor is ready to send data.
Start of Cell. Also known as TX_SOC.
Active high signal is asserted when UTP_OP_DATA
contains the first valid byte of a transmitted cell.
UTOPIA output data. Also known as UTP_TX_DATA. Used
to send data from the processor to an ATM UTOPIA-Level-
2-compliant PHY.
Transmit PHY address bus. Used by the processor when
operating in MPHY mode to poll and select a single PHY at
any given time.
UTOPIA Output data flow control input: Also known as the
TXFULL/CLAV signal.
Used to inform the processor of the ability of each polled
PHY to receive a complete cell. For cell-level flow control
in an MPHY environment, TxClav is an active high tri-
stateable signal from the MPHY to ATM layer. The
UTP_OP_FCI, which is connected to multiple MPHY
devices, will see logic high generated by the PHY, one
clock after the given PHY address is asserted — when a
full cell can be received by the PHY. The UTP_OP_FCI will
see a logic low generated by the PHY one clock cycle, after
the PHY address is asserted — if a full cell cannot be
received by the PHY.
This signal should be pulled high
resistor if not being used.
UTOPIA Receive clock input. Also known as UTP_RX_CLK.
This signal is used to synchronize all UTOPIA-received
inputs to the rising edge of the UTP_IP_CLK.
This signal should be pulled high
resistor when not being utilized in the system.
33.
Description
Document Number: 252479-006US
††
††
††
through a 10-KΩ
through a 10-KΩ
through a 10-KΩ
August 2006
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