EWIXP425BDT Intel, EWIXP425BDT Datasheet - Page 46
EWIXP425BDT
Manufacturer Part Number
EWIXP425BDT
Description
Manufacturer
Intel
Datasheet
1.EWIXP425BDT.pdf
(130 pages)
Specifications of EWIXP425BDT
Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
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Table 16.
Table 17.
Table 18.
Intel
Datasheet
46
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
JTAG Interface (Sheet 1 of 2)
Oscillator Interface
GPIO Interface
OSC_IN
OSC_OUT
†
GPIO[12:0]
GPIO[13]
GPIO[14]
GPIO[15]
†
††
†
Name
Name
JTG_TMS
JTG_TDI
Name
For a legend of the Type codes, see
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
For a legend of the Type codes, see
Power
or Sys
Reset
Reset
Power
or Sys
Reset
Reset
VO
Z
Z
Z
0
VI
Power
or Sys
Reset
Reset
H
H
CLKOUT
Reset
Reset
Post
Post
/VO
VO
VI
Z
Z
Z
Reset
VI/PE
VI/PE
Post
Type
Type
I/O
I/O
I/O
I/O
O
I
Type
Intel
†
†
I
I
†
33.33 MHz, sinusoidal input signal. Can be driven by an oscillator.
33.33 MHz, sinusoidal output signal. Left disconnected when being
driven by an oscillator.
General purpose Input/Output pins. May be configured as an input
or an output. As an input, each signal may be configured a
processor interrupt. Default after reset is to be configured as
inputs.
Should be pulled high
utilized in the system.
General purpose input/output pins. May be configured as an input
or an output. Default after reset is to be configured as inputs.
Should be pulled high
utilized in the system.
Can be configured similar to GPIO Pin 13 or as a clock output.
Configuration as an output clock can be set at various speeds of up
to 33.33 MHz with various duty cycles. Configured as an input,
upon reset.
Should be pulled high
utilized in the system.
Can be configured similar to GPIO Pin 13 or as a clock output.
Configuration as an output clock can be set at various speeds of up
to 33.33 MHz with various duty cycles. Configured as an output,
upon reset. Can be used to clock the expansion interface, after
reset.
Should be pulled high
utilized in the system.
®
IXP42X product line and IXC1100 control plane processors
Table 5 on page
Table 5 on page
Table 5 on page
Test mode select for the IEEE 1149.1 JTAG interface.
Input data for the IEEE 1149.1 JTAG interface.
33.
33.
33.
††
††
††
††
using a 10-KΩ resistor when not being
using a 10-KΩ resistor when not being
though a 10-KΩ resistor when not being
though a 10-KΩ resistor when not being
Description
Description
Description
Document Number: 252479-006US
August 2006
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