FWIXP420ABD Intel, FWIXP420ABD Datasheet - Page 114
FWIXP420ABD
Manufacturer Part Number
FWIXP420ABD
Description
Manufacturer
Intel
Datasheet
1.FWIXP420ABD.pdf
(128 pages)
Specifications of FWIXP420ABD
Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
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Table 64.
Intel
Datasheet
114
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
HPI-16 Simplex Read Accesses Values
Notes:
1.
2.
3.
4.
5.
6.
7.
T
T
T
T
Symbol
cs2hds1val
hds1_pulse
data_setup
add_setup
T
recov
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel
IXP42X Product Line and Intel
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
®
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
Delay from chip select being active and the HDS1 data
strobe being active.
Pulse width of the HDS1 data strobe.
Data is valid from the time from of the falling edge of
HDS1_N to when the data is read.
Time required between successive accesses on the
expansion interface.
IXP42X Product Line and Intel
Intel
®
IXP42X product line and IXC1100 control plane processors—Datasheet
®
Parameter
IXC1100 Control Plane processors has had sufficient time to
®
IXC1100 Control Plane processors has had sufficient time to
Document Number:
Min.
11
3
4
4
2
Max.
45
17
4
5
5
Cycles
Cycles
Cycles
Cycles
Cycles
Units
252479-007US
June 2007
1, 5,
2, 4,
3, 5,
Notes
5,
4,
6
6
®
6
5
6
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