FWIXP420ABD Intel, FWIXP420ABD Datasheet - Page 21
FWIXP420ABD
Manufacturer Part Number
FWIXP420ABD
Description
Manufacturer
Intel
Datasheet
1.FWIXP420ABD.pdf
(128 pages)
Specifications of FWIXP420ABD
Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
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2.1.4
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2.1.6
June 2007
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The APB interface is also used as an alternate-path interface to the NPEs and is used
for NPE code download and configuration.
MII Interfaces
Two industry-standard, media-independent interface (MII) interfaces are integrated
into most of the IXP42X product line and IXC1100 control plane processors with
separate media-access controllers and independent network processing engines. (See
Table 4 on page
The independent NPEs and MACs allow parallel processing of data traffic on the MII
interfaces and off-loading of processing required by the Intel XScale
IXP42X product line and IXC1100 control plane processors are compliant with the IEEE,
802.3 specification.
In addition to two MII interfaces, the IXP42X product line and IXC1100 control plane
processors include a single management data interface that is used to configure and
control PHY devices that are connected to the MII interface.
UTOPIA Level 2
The integrated, UTOPIA Level 2 interface works with a network processing engine, for
several of the IXP42X product line and IXC1100 control plane processors. (See
on page
The UTOPIA Level 2 interface supports a single- or a multiple-physical-interface
configuration with cell-level or octet-level handshaking. The network processing engine
handles segmentation and reassembly of ATM cells, CRC checking/generation, and
transfer of data to/from memory. This allows parallel processing of data traffic on the
UTOPIA Level 2 interface, off-loading processor overhead required by the Intel XScale
processor.
The IXP42X product line and IXC1100 control plane processors are compliant with the
ATM Forum, UTOPIA Level-2 Specification, Revision 1.0.
USB Interface
The integrated USB 1.1 interface is a device-only controller. The interface supports
full-speed operation and 16 endpoints and includes an integrated transceiver.
There are:
PCI Controller
The IXP42X product line and IXC1100 control plane processors’ PCI controller is
compatible with the PCI Local Bus Specification, Rev. 2.2. The PCI interface is 32-bit
compatible bus and capable of operating as either a host or an option (that is, not the
Host) For more information on PCI Controller support and configuration see the Intel
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Developer’s Manual.
®
• Six isochronous endpoints (three input and three output)
• One control endpoints
• Three interrupt endpoints
• Six bulk endpoints (three input and three output)
252479-007US
IXP42X product line and IXC1100 control plane processors
19.)
19.)
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
processor. The
Datasheet
Table 4
®
®
21
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