MT29C8G96MAZAPDJV-5 IT Micron Technology Inc, MT29C8G96MAZAPDJV-5 IT Datasheet
MT29C8G96MAZAPDJV-5 IT
Specifications of MT29C8G96MAZAPDJV-5 IT
Related parts for MT29C8G96MAZAPDJV-5 IT
MT29C8G96MAZAPDJV-5 IT Summary of contents
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... NAND Flash and Mobile LPDDR 168-Ball Package-on-Package (PoP) MCP Combination Memory (TI OMAP™) MT29C4G48MAYAPAKQ-5 IT, MT29C4G48MAZAPAKQ-5 IT, MT29C4G48MAZAPAKQ-6 IT, MT29C4G96MAZAPCJG-5 IT, MT29C4G96MAZAPCJG-6 IT, MT29C8G96MAZAPDJV-5 IT, MT29C8G96MAZAPDJV-6 IT Features • Micron ® NAND Flash and LPDDR components • RoHS-compliant, “green” package • Separate NAND Flash and LPDDR interfaces • ...
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Part Numbering Information Micron NAND Flash and LPDRAM devices are available in different configurations and densities. The MCP/PoP part numbering guide is available at www.micron.com/numbering. Figure 2: Part Number Chart Micron Technology Product Family NAND Flash Density LPDRAM Density Operating ...
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Contents MCP General Description ............................................................................................................................... 11 Ball Assignments and Descriptions ................................................................................................................. 12 Electrical Specifications .................................................................................................................................. 16 Device Diagrams ............................................................................................................................................ 17 Package Dimensions ...................................................................................................................................... 19 4Gb, 8Gb: x8, x16 NAND Flash Memory ........................................................................................................... 22 Features ..................................................................................................................................................... 22 General Description ....................................................................................................................................... 23 ...
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Erase Operations ............................................................................................................................................ 80 ERASE BLOCK (60h-D0h) ............................................................................................................................ 80 ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 81 Internal Data Move Operations ....................................................................................................................... 82 READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................ 83 PROGRAM FOR INTERNAL DATA MOVE (85h–10h) .................................................................................... 84 PROGRAM FOR INTERNAL ...
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Initialization ................................................................................................................................................. 169 Standard Mode Register ................................................................................................................................. 172 Burst Length ............................................................................................................................................. 173 Burst Type ................................................................................................................................................ 173 CAS Latency ............................................................................................................................................. 174 Operating Mode ........................................................................................................................................ 175 Extended Mode Register ................................................................................................................................ 176 Temperature-Compensated Self Refresh ................................................................................................... 176 Partial-Array Self Refresh .......................................................................................................................... 177 Output ...
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List of Tables Table 1: x8, x16 NAND Ball Descriptions ........................................................................................................ 13 Table 2: x32 LPDDR Ball Descriptions ............................................................................................................ 14 Table 3: Non-Device-Specific Descriptions .................................................................................................... 15 Table 4: Absolute Maximum Ratings .............................................................................................................. 16 Table 5: Recommended Operating Conditions ............................................................................................... 16 ...
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Table 51: DM Operation Truth Table ............................................................................................................ 157 Table 52: Truth Table – Current State Bank n – Command to Bank n .............................................................. 163 Table 53: Truth Table – Current State Bank n – Command to Bank m ............................................................. 165 ...
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List of Figures Figure 1: PoP Block Diagram ........................................................................................................................... 1 Figure 2: Part Number Chart ............................................................................................................................ 2 Figure 3: 168-Ball VFBGA (NAND x8, x16; LPDDR x32) Ball Assignments ......................................................... 12 Figure 4: 168-Ball (Single LPDDR) Functional Block Diagram .......................................................................... 17 ...
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Figure 51: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ............................................................... 83 Figure 52: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ................... 83 Figure 53: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ....................................................... 84 Figure 54: ...
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Figure 102: Functional Block Diagram (x16) .................................................................................................. 136 Figure 103: Functional Block Diagram (x32) .................................................................................................. 137 Figure 104: Typical Self Refresh Current vs. Temperature ............................................................................... 146 Figure 105: ACTIVE Command ..................................................................................................................... 158 Figure 106: READ Command ........................................................................................................................ 159 Figure 107: ...
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MCP General Description Micron package-on-package (PoP) MCP products combine NAND Flash and Mobile LPDRAM devices in a single MCP. These products target mobile applications with low- power, high-performance, and minimal package-footprint design requirements. The NAND Flash and Mobile LPDRAM devices ...
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Ball Assignments and Descriptions Figure 3: 168-Ball VFBGA (NAND x8, x16; LPDDR x32) Ball Assignments DNU DNU DQ17 V DQ19 DM2 V DDQ B DNU DNU DQ16 V DQ18 DQS2 V SSQ C ...
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Table 1: x8, x16 NAND Ball Descriptions Symbol CE0#, CE1# I/O[15:0] Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 ...
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Table 2: x32 LPDDR Ball Descriptions Symbol BA0, BA1 CK, CK# CKE0, CKE1 CS0#, CS1# DM[3:0] DQ[31:0] DQS[3:0] 1. Balls marked RFU may or may not be connected internally. These balls should not be Note: used. Contact factory for details. ...
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Table 3: Non-Device-Specific Descriptions Symbol Symbol Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR ...
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Electrical Specifications Table 4: Absolute Maximum Ratings Parameters/Conditions relative to V Voltage on any pin relative to V Storage temperature range Note: 1. Supply voltage references V Stresses greater than those listed under “Absolute Maximum ...
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Device Diagrams Figure 4: 168-Ball (Single LPDDR) Functional Block Diagram CE0# CLE ALE RE# WE# WP# LOCK CS0# CK CK# CKE0 RAS# CAS# WE# Address, BA0, BA1 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP ...
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Figure 5: 168-Ball (Dual LPDDR) Functional Block Diagram CS0, CS1# CKE0, CKE1 Address, BA0, BA1 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP CE0# CLE ALE NAND Flash RE# WE# WP# CK ...
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Package Dimensions Figure 6: 168-Ball VFBGA (Package Code: JG) Seating plane A 0.08 A 168X Ø0.34 Solder ball material: SAC105. Dimensions apply to solder balls post- reflow on Ø0. ...
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Figure 7: 168-Ball VFBGA (Package Code: JV) Seating plane A 0.08 A 168X Ø0.34 Solder ball material: SAC105. Dimensions apply to solder balls post- reflow on Ø0. ...
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Figure 8: 168-Ball WFBGA (Package Code: KQ) Seating plane A 0.08 A 168X Ø0.34 Solder ball material: SAC105. Dimensions apply to solder balls post- reflow on Ø0. ...
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NAND Flash Memory Features • Open NAND Flash Interface (ONFI) 1.0-compliant • Single-level cell (SLC) technology • Organization – Page size x8: 2112 bytes (2048 + 64 bytes) – Page size x16: 1056 words (1024 + ...
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See Electrical Specifications – Program/Erase Characteristics (page 121) for t PROG_ECC specifications. 3. These commands supported only with ECC disabled. General Description Micron NAND Flash devices include an asynchronous data interface for high-perform- ance I/O operations. These devices use ...
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Architecture These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. The commands received at the I/O control circuits are latched by a command register ...
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Device and Array Organization Figure 10: Array Organization – MT29F4G08 (x8) Cache Register 2048 Data Register 2048 2048 blocks 1 block per plane 4096 blocks per device Plane of even-numbered blocks ( ..., 4092, 4094) Table 6: ...
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Figure 11: Array Organization – MT29F4G16 (x16) Cache Register 1024 Data Register 1024 2048 blocks per plane 1 block 4096 blocks per device Plane of even-numbered blocks ( ..., 4092, 4094) Table 7: Array Addressing – MT29F4G16 ...
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Figure 12: Array Organization – MT29F8G08 (x8) 2112 bytes Cache Register 2048 64 Data Register 2048 64 2048 blocks per plane 1 block 4096 blocks per die Plane 0: even- numbered blocks numbered blocks ( ..., 4092, ...
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Figure 13: Array Organization – MT29F8G16 (x16) 1056 words Cache Register 1024 32 Data Register 1024 32 2048 blocks per plane 1 block 4096 blocks per die Plane 0: even- numbered blocks numbered blocks ( ..., 4092, ...
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Asynchronous Interface Bus Operation The bus on the device is multiplexed. Data I/O, addresses, and commands all share the same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and com- mands are always supplied on I/O[7:0]. ...
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Figure 14: Asynchronous Command Latch Cycle CLE CE# WE# ALE I/Ox PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation t t CLS CLH ...
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Asynchronous Addresses An asynchronous address is written from I/O[7:0] to the address register on the rising edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH. Bits that are not part of the ...
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Asynchronous Data Input Data is written from I/O[7:0] to the cache register of the selected die (LUN) on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH. Data input is ...
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Asynchronous Data Output Data can be output from a die (LUN READY state. Data output is supported following a READ operation from the NAND Flash array. Data is output from the cache register of the ...
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Figure 18: Asynchronous Data Output Cycles (EDO Mode) CE# RE# t CEA I/ RDY Write Protect# The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations to a target. When WP# is LOW, PROGRAM and ERASE ...
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R/B# outputs to be OR-tied. Typically, R/B# is connected to an interrupt pin on the system controller. The combination of Rp and capacitive loading of the R/B# circuit determines the rise time of the R/B# signal. The ...
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Figure 20: Fall and Rise (3.3V V 3.50 3.00 2.50 2.00 V 1.50 1.00 0.50 0. Fall and Notes Rise dependent on external capacitance and resistive loading and output transistor im- pedance ...
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Figure 22 (mA) Figure 23: I vs. Rp (1. (mA) PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP ...
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Figure 24: TC vs. Rp T(ns) PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation 1200 1000 800 600 400 200 0 0 2000 4000 38 Micron Technology, Inc. ...
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Device Initialization Micron NAND Flash devices are designed to prevent data corruption during power tran- sitions. V protection during power transitions.) When ramping V to initialize the device: 1. Ramp V 2. The host must wait for R/ ...
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Command Definitions Table 11: Command Set Command Command Cycle #1 Reset Operations RESET FFh Identification Operation READ ID 90h READ PARAMETER PAGE ECh READ UNIQUE ID EDh Feature Operations GET FEATURES EEh SET FEATURES EFh Status Operations READ STATUS 70h ...
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Table 11: Command Set (Continued) Command Command Cycle #1 Block Lock Operations BLOCK UNLOCK LOW 23h BLOCK UNLOCK HIGH 24h BLOCK LOCK 2Ah BLOCK LOCK-TIGHT 2Ch BLOCK LOCK READ 7Ah STATUS One-Time Programmable (OTP) Operations OTP DATA LOCK BY 80h ...
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Table 12: Two-Plane Command Set (Continued) Note 4 applies to all parameters and conditions Com- mand Command Cycle #1 PROGRAM PAGE 80h TWO-PLANE PROGRAM PAGE 80h CACHE MODE TWO- PLANE PROGRAM FOR TWO- 85h PLANE INTERNAL DA- TA MOVE BLOCK ...
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Reset Operations RESET (FFh) The RESET command is used to put the memory device into a known condition and to abort the command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the ...
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Identification Operations READ ID (90h) The READ ID (90h) command is used to read identifier codes programmed into the tar- get. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing 90h ...
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READ ID Parameter Tables Table 13: READ ID Parameters for Address 00h b = binary hexadecimal Options Byte 0 – Manufacturer ID Manufacturer Micron Byte 1 – Device ID MT29F4G08ABADA 4Gb, x8, 3.3V MT29F4G16ABADA 4Gb, x16, 3.3V MT29F4G08ABBDA ...
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Table 13: READ ID Parameters for Address 00h (Continued binary hexadecimal Options Byte value MT29F4G08ABADA MT29F4G16ABADA MT29F4G08ABBDA MT29F4G16ABBDA MT29F8G08ADBDA MT29F8G16ADBDA MT29F8G08ADADA MT29F8G16ADADA Byte 4 Internal ECC level 4-bit ECC/512 (main (spare (parity) ...
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READ PARAMETER PAGE (ECh) The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing ...
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Bare Die Parameter Page Data Structure Tables Table 15: Parameter Page Data Structure Byte Description 0–3 Parameter page signature 4–5 Revision number 6–7 Features supported 8–9 Optional commands supported 10–31 Reserved 32–43 Device manufacturer 44–63 Device model 64 Manufacturer ID ...
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Table 15: Parameter Page Data Structure (Continued) Byte Description 96–99 Number of blocks per unit 100 Number of logical units 101 Number of address cycles 102 Number of bits per cell 103–104 Bad blocks maximum per unit 105–106 Block endurance ...
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Table 15: Parameter Page Data Structure (Continued) Byte Description 131–132 Program cache timing mode support t 133–134 PROG (MAX) page program time t 135–136 BERS (MAX) block erase time t 137–138 R (MAX) page read time t 139–140 CCs (MIN) ...
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READ UNIQUE ID (EDh) The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EDh ...
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Feature Operations The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the target's default power-on behavior. These commands use a one-byte feature address to determine which subfeature parameters will be read or modified. Each feature address ...
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Table 17: Feature Address 90h – Array Operation Mode Subfeature Parameter Options 1/O7 P1 Operation Normal mode option OTP operation OTP protection Disable ECC Enable ECC P2 Reserved P3 Reserved P4 Reserved Note: 1. These bits are reset to 00h ...
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GET FEATURES (EEh) The GET FEATURES (EEh) command reads the subfeature parameters (P1–P4) from the specified feature address. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EEh to the command ...
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Table 18: Feature Addresses 01h: Timing Mode Subfeature Parameter Options P1 Timing mode Mode 0 (default) Mode 1 Mode 2 Mode 3 Mode 4 Mode The timing mode feature address is used to change the ...
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Table 19: Feature Addresses 80h: Programmable I/O Drive Strength Subfeature Parameter Options P1 I/O drive strength Full (default) Three-quarters One-half One-quarter The programmable drive strength feature address is used to change the default I/O Note: drive ...
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Status Operations Each die (LUN) provides its status independently of other die (LUNs) on the same tar- get through its 8-bit status register. After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued, status register output is ...
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READ STATUS (70h) The READ STATUS (70h) command returns the status of the last-selected die (LUN target. This command is accepted by the last-selected die (LUN) even when it is busy (RDY = 0). If there is only ...
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Figure 34: READ STATUS ENHANCED (78h) Operation Cycle type I/Ox PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Command Address Address Address t WHR 78h Micron Technology, Inc. ...
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Column Address Operations The column address operations affect how data is input to and output from the cache registers within the selected die (LUNs). These features provide host flexibility for man- aging data, especially when the host internal buffer is ...
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RANDOM DATA READ TWO-PLANE (06h-E0h) The RANDOM DATA READ TWO-PLANE (06h-E0h) command enables data output on the addressed die’s (LUN’s) cache register at the specified column address. This com- mand is accepted by a die (LUN) when it is ready ...
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RANDOM DATA INPUT (85h) The RANDOM DATA INPUT (85h) command changes the column address of the selec- ted cache register and enables data input on the last-selected die (LUN). This command is accepted by the selected die (LUN) when it ...
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PROGRAM FOR INTERNAL DATA INPUT (85h) The PROGRAM FOR INTERNAL DATA INPUT (85h) command changes the row address (block and page) where the cache register contents will be programmed in the NAND Flash array. It also changes the column address ...
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Figure 38: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation As defined for PAGE (CACHE) PROGRAM Cycle type I/O[7: RDY PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP ...
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Read Operations The READ PAGE (00h-30h) command, when issued by itself, reads one page from the NAND Flash array to its cache register and enables data output for that cache register. During data output the following commands can be used ...
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Two-Plane Read Operations Two-plane read page operations improve data throughput by copying data from more than one plane simultaneously to the specified cache registers. This is done by prepend- ing one or more READ PAGE TWO-PLANE (00h-00h-30h) commands in front ...
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For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time, t RCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and RESET (FFh). When RDY = 1 ...
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READ PAGE (00h-30h) com- mand. The RANDOM DATA READ TWO-PLANE (06h-E0h) command is used to enable data output in the other cache registers. Figure 39: READ PAGE (00h-30h) Operation Cycle ...
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Figure 41: READ PAGE CACHE SEQUENTIAL (31h) Operation Cycle type Command Address x5 Command I/O[7:0] 00h Page Address M 30h t WB RDY READ PAGE CACHE RANDOM (00h-31h) The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and ...
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Figure 42: READ PAGE CACHE RANDOM (00h-31h) Operation Cycle type Command Address x5 Command 00h Page Address M 30h I/O[7:0] RDY Cycle type D Command Address x5 OUT I/O[7:0] Dn 00h Page Address P RDY 1 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – ...
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READ PAGE CACHE LAST (3Fh) The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and copies a page from the data register to the cache register. This command is accepted by the die (LUN) when it ...
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READ PAGE TWO-PLANE 00h-00h-30h The READ PAGE TWO-PLANE (00h-00h-30h) operation is similar to the PAGE READ (00h-30h) operation. It transfers two pages of data from the NAND Flash array to the data registers. Each page must be from a different ...
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Figure 44: READ PAGE TWO-PLANE (00h-00h-30h) Operation CLE WE# ALE RE# Page address M Col Col 00h I/Ox add 1 add 2 Column address J R/B# CLE WE# ALE RE# I/ OUT OUT Plane 0 data ...
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Program Operations Program operations are used to move data from the cache or data registers to the NAND array. During a program operation the contents of the cache and/or data regis- ters are modified by the internal control logic. Within ...
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PROGRAM PAGE (80h-10h) The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache register, and moves the data from the cache register to the specified block and page ad- dress in the array of the selected ...
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PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die (LUN) when it is ready (RDY =1, ARDY = 1 also accepted by the die ...
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Figure 46: PROGRAM PAGE CACHE (80h–15h) Operation (Start) Cycle type Command Address Address I/O[7:0] 80h C1 C2 RDY Cycle type Command Address Address I/O[7:0] 80h C1 C2 RDY 1 Figure 47: PROGRAM PAGE CACHE (80h–15h) Operation (End) As defined for ...
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PROGRAM PAGE TWO-PLANE (80h-11h) The PROGRAM PAGE TWO-PLANE (80h-11h) command enables the host to input data to the addressed plane's cache register and queue the cache register to ultimately be moved to the NAND Flash array. This command can be ...
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Figure 48: PROGRAM PAGE TWO-PLANE (80h–11h) Operation Cycle type Command Address Address I/O[7:0] 80h C1 C2 RDY PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP D Address Address Address IN t ADL ...
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Erase Operations Erase operations are used to clear the contents of a block in the NAND Flash array to prepare its pages for program operations. Erase Operations The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK TWO- ...
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ERASE BLOCK TWO-PLANE (60h-D1h) The ERASE BLOCK TWO-PLANE (60h-D1h) command queues a block in the specified plane to be erased in the NAND Flash array. This command can be issued one or more times. Each time a new plane address ...
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Internal Data Move Operations Internal data move operations make it possible to transfer data within a device from one page to another using the cache register. This is particularly useful for block man- agement and wear leveling. The INTERNAL DATA ...
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READ FOR INTERNAL DATA MOVE (00h-35h) The READ FOR INTERNAL DATA MOVE (00h-35h) command is functionally identical to the READ PAGE (00h-30h) command, except that 35h is written to the command reg- ister instead of 30h. Though it is not ...
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Figure 53: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled t R_ECC R/B# Address I/O[7:0] 00h 35h (5 cycles) Source address Figure 54: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled t R_ECC R/B# Address I/O[7:0] ...
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Figure 56: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) Cycle type Command Address I/O[7:0] 85h RDY Cycle type Command I/O[7:0] 85h RDY 1 PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) The PROGRAM FOR INTERNAL DATA MOVE ...
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Block Lock Feature The block lock feature protects either the entire device or ranges of blocks from being programmed and erased. Using the block lock feature is preferable to using WP# to pre- vent PROGRAM and ERASE operations. Block lock ...
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Figure 58: Flash Array Protected: Invert Area Bit = 0 Block 4095 Block 4094 Block 4093 Block 4092 Block 4091 Block 4090 Block 4089 Block 4088 Block 4087 . . . . . . . . . . . . ...
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Table 22: Block Lock Address Cycle Assignments 1 ALE Cycle I/O[15:8] I/O7 First LOW BA7 Second LOW BA15 Third LOW LOW 1. I/O[15:8] is applicable only for x16 devices. Notes: 2. Invert area bit is applicable for 24h command; it ...
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LOCK (2Ah) By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from PROGRAM and ERASE operations. If portions of the device are unlocked using the UN- LOCK (23h) command, they can be locked again ...
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LOCK TIGHT (2Ch) The LOCK TIGHT (2Ch) command prevents locked blocks from being unlocked and al- so prevents unlocked blocks from being locked. When this command is issued, the UNLOCK (23h) and LOCK (2Ah) commands are disabled. This provides an ...
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Figure 63: PROGRAM/ERASE Issued to Locked Block R/B# PROGRAM or ERASE I/Ox BLOCK LOCK READ STATUS (7Ah) The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection status of individual blocks. The address cycles have the same ...
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Figure 65: BLOCK LOCK Flowchart Entire NAND Flash array locked tight Unlocked range WP# LOW >100ns or LOCK Cmd Locked range Unlocked range UNLOCK Cmd with invert area LOCK TIGHT Cmd bit = 1 with WP# and LOCK HIGH Unlocked ...
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One-Time Programmable (OTP) Operations This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Thirty full pages (2112 bytes per page) of OTP data are available on the device, and the entire range is guaranteed to ...
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OTP DATA PROGRAM (80h-10h) The OTP DATA PROGRAM (80h-10h) command is used to write data to the pages within the OTP area. An entire page can be programmed at one time page can be partially programmed up to ...
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RANDOM DATA INPUT (85h) After the initial OTP data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of ...
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Figure 67: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Opera- tion Mode) CLE CE WE# ALE RE# Col Col OTP I/Ox 00h 80h 1 add1 page add2 SERIAL DATA INPUT command R/B# OTP DATA ...
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Figure 68: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) CLE CE WE# ALE RE# Col I/Ox 80h 00h OTP DATA PROTECT command R/B# 1. OTP data is protected following a good status confirmation. Note: PDF: 09005aef83ba4387 ...
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OTP DATA READ (00h-30h) To read data from the OTP area, set the device to OTP operation mode, then issue the PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area whether the area is ...
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Figure 70: OTP DATA READ with RANDOM DATA READ Operation CLE CE# WE# ALE RE# Col Col OTP I/Ox 00h add 1 add 2 page Column address n R/B# Note: 1. The OTP page must be within the range 02h–1Fh. ...
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Two-Plane Operations Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each plane contains a cache register and a data register independent of the other planes. The planes are addressed via the low-order block address bits. Specific ...
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Figure 71: TWO-PLANE PAGE READ CLE WE# ALE RE# Page address M Col Col 00h I/Ox add 1 add 2 Column address J R/B# CLE WE# ALE RE# I/ OUT OUT Plane 0 data R/B# 1 ...
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Figure 72: TWO-PLANE PAGE READ with RANDOM DATA READ R/B# RE# 00h Address (5 cycles) 00h I/Ox Plane 0 address R/B# RE# I/Ox 06h Address (5 cycles) E0h Plane 1 address 1 Figure 73: TWO-PLANE PROGRAM PAGE R/B# I/Ox 80h ...
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Figure 74: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT R/B# I/Ox 80h Address (5 cycles) Data 1st-plane address R/B# I/Ox 85h Address (2 cycles) Data Different column address than previous 1 5 address cycles, for 2nd plane only Unlimited number ...
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Figure 75: TWO-PLANE PROGRAM PAGE CACHE MODE R/B# 80h Address/data input I/Ox 1st plane R/B# 80h Address/data input I/Ox 1st plane 1 R/B# 80h Address/data input I/Ox 1st plane 2 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash ...
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Figure 76: TWO-PLANE INTERNAL DATA MOVE R/B# 00h Address (5 cycles) I/Ox 1st-plane source R/B# 85h Address (5 cycles) I/Ox 2nd-plane destination 1 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP t ...
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Figure 77: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ R/B# RE# I/Ox 00h Address (5 cycles) 00h 1st-plane source R/B# RE# I/Ox Data output Data from 1 2nd-plane source R/B# RE# I/Ox 85h Address (5 cycles) 11h 1st-plane ...
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Figure 78: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT R/B# 00h 00h I/Ox Address (5 cycles) 1st-plane source t DBSY R/B# 85h I/Ox Address (5 cycles) 2nd-plane destination 1 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash ...
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Figure 79: TWO-PLANE BLOCK ERASE CLE CE# WE# ALE R/B# RE# I/Ox Address input (3 cycles) 60h 1st plane Figure 80: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle CE# CLE WE# ALE RE# I/Ox 78h PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball ...
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Interleaved Die (Multi-LUN) Operations In devices that have more than one die (LUN) per target possible to improve per- formance by interleaving operations between the die (LUNs). An interleaved die (multi- LUN) operation is one that is issued ...
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Error Management Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks (NVB) of the total available blocks. This means the die (LUNs) could have blocks that are invalid when shipped from the factory. An ...
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Table 24: Error Management Details (Continued) Description Minimum ECC with internal ECC enabled Minimum required ECC for block 0 if PROGRAM/ ERASE cycles are less than 1000 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP ...
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Internal ECC and Spare Area Mapping for ECC Internal ECC enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256 words (x16) of the main area and 4 bytes (x8 words (x16) of metadata I ...
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Figure 82: Spare Area Mapping (x16) Max word Min word ECC Protected Address Address 0FFh 000h Yes 1FFh 100h Yes 2FFh 200h Yes 3FFh 300h Yes 400h 400h No 401h 401h No 403h 402h Yes 407h 404h Yes 408h 408h ...
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Electrical Specifications Stresses greater than those listed can cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of ...
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Table 28: Capacitance Notes 1–3 apply to all parameters and conditions Description Input capacitance Input/output capacitance (I/O) 1. These parameters are verified in device characterization and are not 100% tested. Notes: 2. Test conditions Capacitance (C Table 29: ...
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Electrical Specifications – DC Characteristics and Operating Conditions Table 30: DC Characteristics and Operating Conditions (3.3V) Parameter Conditions t t Sequential READ current (MIN); CE PROGRAM current ERASE current Standby current (TTL) WP# = 0V/V ...
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Table 31: DC Characteristics and Operating Conditions (1.8V) Parameter Conditions t t Sequential READ current (MIN); CE PROGRAM current ERASE current Standby current (TTL) WP# = 0V/V Standby current (CMOS) CE WP# = ...
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Electrical Specifications – AC Characteristics and Operating Conditions Table 32: AC Characteristics: Command, Data, and Address Input (3.3V) Note 1 applies to all Parameter ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time ...
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Table 34: AC Characteristics: Normal Operation (3.3V) Note 1 applies to all Parameter ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay CE# HIGH to output hold Output High-Z to RE# LOW READ ...
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Table 35: AC Characteristics: Normal Operation (1.8V) (Continued) Note 1 applies to all Parameter RE# HIGH to output High-Z RE# LOW to output hold RE# pulse width Ready to RE# LOW Reset time (READ/PROGRAM/ERASE) WE# HIGH to busy WE# HIGH ...
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Electrical Specifications – Program/Erase Characteristics Table 36: Program/Erase Characteristics Parameter Number of partial-page programs BLOCK ERASE operation time Busy time for PROGRAM CACHE operation Cache read busy time Busy time for SET FEATURES and GET FEATURES operations Busy time for ...
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Asynchronous Interface Timing Diagrams Figure 83: RESET Operation CLE CE WE# R/B# FFh I/O[7:0] RESET command Figure 84: READ STATUS Cycle CLE CE# WE# RE# I/O[7:0] PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR ...
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Figure 85: READ STATUS ENHANCED Cycle t CS CE# t CLS t CLH CLE t WP WE# ALE RE I/O[7:0] 78h Figure 86: READ PARAMETER PAGE CLE WE ALE RE# I/O[7:0] ECh 00h R/B# ...
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Figure 87: READ PAGE CLE CE WE# ALE RE# Col Col I/Ox 00h add 1 add 2 RDY PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams ...
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Figure 88: READ PAGE Operation with CE# “Don’t Care” CLE CE# RE# ALE RDY WE# I/Ox 00h Address (5 cycles) PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams ...
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Figure 89: RANDOM DATA READ CLE CE# WE# ALE t RC RE RDY PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams t RHW ...
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Figure 90: READ PAGE CACHE SEQUENTIAL CLE t CLS t CLH CE WE# ALE RE Row Col Col I/Ox 00h add 1 add 2 add 1 Column address 00h RDY ...
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Figure 91: READ PAGE CACHE RANDOM CLE t CLS t CLH CE WE# ALE RE Col Col I/Ox 00h add 1 add 2 Column address 00h RDY CLE CE# WE# ...
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Figure 92: READ ID Operation CLE CE# WE# ALE RE# I/Ox 90h 00h or 20h Address, 1 cycle Figure 93: PROGRAM PAGE Operation CLE CE WE# ALE RE# Col Col I/Ox 80h add 1 add 2 RDY PDF: ...
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Figure 94: PROGRAM PAGE Operation with CE# “Don’t Care” CLE CE# WE# ALE I/Ox 80h Address (5 cycles) Figure 95: PROGRAM PAGE Operation with RANDOM DATA INPUT CLE CE WE# ALE RE# Col Col Row Row I/Ox 80h ...
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Figure 96: PROGRAM PAGE CACHE CLE CE WE# ALE RE# Row Row Row Col Col I/Ox 80h add 1 add 2 add 1 add 2 add 3 RDY Last page - 1 Figure 97: PROGRAM PAGE CACHE Ending ...
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Figure 98: INTERNAL DATA MOVE CLE CE WE# ALE RE# Col Col Row Row I/Ox 00h add 1 add 2 add 1 add 2 RDY Figure 99: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled t R_ECC R/B# ...
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Figure 100: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled t R_ECC R/B# Address I/O[7:0] 00h 35h 70h (5 cycles) Source address SR bit READ successful SR bit READ error ...
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Mobile LPDDR SDRAM Features • • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and ...
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General Description The 2Gb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-ac- cess memory containing 2,147,483,648 bits internally configured as a quad-bank DRAM. Each of the x16’s 536,870,912-bit banks is organized as 16,384 rows by 2048 ...
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Functional Block Diagrams Figure 102: Functional Block Diagram (x16) CKE CK# CK CS# Control logic WE# CAS# Refresh RAS# counter Standard mode register Extended mode register Row- address Mux 2 Address Address BA0, BA1 register 2 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – ...
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Figure 103: Functional Block Diagram (x32) CKE CK# CK Control CS# logic WE# CAS# RAS# Refresh counter Standard mode register Extended mode Row- register address MUX 2 Address, Address BA0, BA1 register 2 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 ...
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Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections ...
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Table 39: AC/DC Electrical Characteristics and Operating Conditions (Continued) Notes 1–5 apply to all parameters/conditions in this table; V Parameter/Condition Output leakage current (DQ are disabled; 0V ≤ V ≤ V OUT DDQ Operating temperature Commercial Industrial Automotive 1. All ...
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Table 40: Capacitance (x16, x32) Note 1 applies to all the parameters in this table Parameter Input capacitance: CK, CK# Delta input capacitance: CK, CK# Input capacitance: command and address Delta input capacitance: command and address Input/output capacitance: DQ, DQS, ...
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Electrical Specifications – I Table 41: I Specifications and Conditions, –40°C to +85°C (x16) DD Notes 1–5 apply to all the parameters/conditions in this table; V Parameter/Condition Operating 1 bank active precharge current (MIN); CKE is HIGH; ...
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Table 42: I Specifications and Conditions, –40°C to +85°C (x32) DD Notes 1–5 apply to all the parameters/conditions in this table; V Parameter/Condition Operating 1 bank active precharge current (MIN); CKE is HIGH HIGH between ...
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Table 43: I Specifications and Conditions, –40°C to +105°C (x16) DD Notes 1–5 apply to all the parameters/conditions in this table; V Parameter/Condition Operating 1 bank active precharge current (MIN); CKE is HIGH HIGH between ...
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Table 44: I Specifications and Conditions, –40°C to +105°C (x32) DD Notes 1–5 apply to all the parameters/conditions in this table; V Parameter/Condition Operating 1 bank active precharge current (MIN); CKE is HIGH HIGH between ...
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Table 45 Specifications and Conditions DD Notes 1–5, 7, and 12 apply to all the parameters/conditions in this table; V Parameter/Condition Self refresh CKE = LOW (MIN); Address and control inputs are stable; ...
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Figure 104: Typical Self Refresh Current vs. Temperature 1600 Full Array 1/2 Array 1500 1/4 Array 1/8 Array 1400 1/16 Array 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 -40 -30 -20 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf ...
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Electrical Specifications – AC Operating Conditions Table 46: Electrical Characteristics and Recommended AC Operating Conditions Notes 1–9 apply to all the parameters in this table; V Parameter Symbol t Access window from CK/CK# CL ...
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Table 46: Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes 1–9 apply to all the parameters in this table; V Parameter Symbol Data valid output window n/a (DVW) t Half-clock period HP t Data-out High ...
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Table 46: Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes 1–9 apply to all the parameters in this table; V Parameter Symbol t PRECHARGE command pe- RP riod t DQS read preamble RPRE ...
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The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference voltage level for signals other than CK/ CK and CK# input ...
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The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will de- grade accordingly. 26. At least 1 clock cycle is required ...
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Output Drive Characteristics Table 47: Target Output Drive Characteristics (Full Strength) Notes 1–2 apply to all values; characteristics are specified under best and worst process variations/conditions Voltage (V) Min 0.00 0.00 0.10 2.80 0.20 5.60 0.30 8.40 0.40 11.20 0.50 ...
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Table 48: Target Output Drive Characteristics (Three-Quarter Strength) Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions Voltage (V) Min 0.00 0.00 0.10 1.96 0.20 3.92 0.30 5.88 0.40 7.84 0.50 9.80 0.60 11.76 ...
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Table 49: Target Output Drive Characteristics (One-Half Strength) Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions Voltage (V) Min 0.00 0.00 0.10 1.27 0.20 2.55 0.30 3.82 0.40 5.09 0.50 6.36 0.60 7.64 ...
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Functional Description The Mobile LPDDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the ...
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Commands A quick reference for available commands is provided in Table 50 and Table 51 (page 157), followed by a written description of each command. Three additional truth tables (Table 52 (page 163), Table 53 (page 165), and Table 54 ...
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Table 51: DM Operation Truth Table Name (Function) Write enable Write inhibit 1. Used to mask write data; provided coincident with the corresponding data. Notes: 2. All states and sequences not shown are reserved and/or illegal. DESELECT The DESELECT function ...
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Figure 105: ACTIVE Command CK# CKE RAS# CAS# WE# Address BA0, BA1 READ The READ command is used to initiate a burst read access to an active row. The values on the BA0 and BA1 inputs select the bank; the ...
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Figure 106: READ Command CK# RAS# CAS# WE# Address A10 BA0, BA1 enable auto precharge; DIS AP = disable auto precharge. Note: WRITE The WRITE command is used to initiate a burst write access to an ...
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Figure 107: WRITE Command CK# CKE RAS# CAS# WE# Address A10 BA0, BA1 enable auto precharge; DIS AP = disable auto precharge. Note: PRECHARGE The PRECHARGE command is used to deactivate the open row in a ...
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Figure 108: PRECHARGE Command CK# CKE RAS# CAS# WE# Address A10 BA0, BA1 1. If A10 is HIGH, bank address becomes “Don’t Care.” Note: BURST TERMINATE The BURST TERMINATE command is used to truncate READ bursts with auto pre- charge ...
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SELF REFRESH The SELF REFRESH command is used to place the device in self refresh mode; self re- fresh mode is used to retain data in the memory device while the rest of the system is powered down. When in ...
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Truth Tables Table 52: Truth Table – Current State Bank n – Command to Bank n Notes 1–6 apply to all parameters in this table Current State CS# RAS# Any Idle ...
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Read with auto-precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when be in the idle state. Write with auto-precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends ...
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Table 53: Truth Table – Current State Bank n – Command to Bank m Notes 1–6 apply to all parameters in this table Current State CS# RAS# Any Idle X X Row activating active, ...
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PRE- CHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when precharge was disabled. The access ...
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Table 54: Truth Table – CKE Notes 1–4 apply to all parameters in this table Current State CKE Active power-down L Deep power-down L Precharge power-down L Self refresh L Active power-down L Deep power-down L Precharge ...
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State Diagram Figure 110: Simplified State Diagram Power Power on applied PRE PREALL LMR LMR EMR WRITE WRITE A PRE ACT = ACTIVE AREF = AUTO REFRESH BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down DPD ...
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Initialization Prior to normal operation, the device must be powered up and initialized in a prede- fined manner. Using initialization procedures other than those specified will result in undefined operation. If there is an interruption to the device power, the ...
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Figure 111: Initialize and Load Mode Registers ( ( ) ) DDQ T0 CK LVCMOS HIGH LEVEL ( ( ) ) CKE ( ( ...
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Figure 112: Alternate Initialization with CKE LOW ( ( ) ) DDQ CK LVCMOS ( ( CKE LOW level ) ) ( ...
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Standard Mode Register The standard mode register bit definition enables the selection of burst length, burst type, CAS latency (CL), and operating mode, as shown in Figure 113. Reserved states should not be used as this may result in setting ...
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Burst Length Read and write accesses to the device are burst-oriented, and the burst length (BL) is programmable. The burst length determines the maximum number of column loca- tions that can be accessed for a given READ or WRITE command. ...
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Table 55: Burst Definition Table (Continued) Burst Length Starting Column Address ...
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Figure 114: CAS Latency CK# Command DQS DQ CK# Command DQS DQ Operating Mode The normal operating mode is selected by issuing a LOAD MODE REGISTER command with bits A[n:7] each set to zero, and bits A[6:0] set to the ...
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Extended Mode Register The EMR controls additional functions beyond those set by the mode registers. These additional functions include drive strength, TCSR, and PASR. The EMR is programmed via the LOAD MODE REGISTER command with BA0 = 0 and BA1 ...
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Partial-Array Self Refresh For further power savings during self refresh, the partial-array self refresh (PASR) fea- ture enables the controller to select the amount of memory to be refreshed during self refresh. The refresh options include: • Full array: banks ...
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Status Read Register The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh multiplier, width type, and density of the device, as shown in Figure 117 (page 179). The SRR is read via the LOAD ...
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Figure 117: Status Register Definition DQ31...DQ16 DQ15 DQ14 DQ13 S31..S16 S15 S14 S13 31.. Density Reserved S15 S14 S13 Density 128Mb 256Mb 512Mb 1Gb ...
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Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the device, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row ...
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READ Operation READ burst operations are initiated with a READ command, as shown in Figure 106 (page 159). The starting column and bank addresses are provided with the READ com- mand, and auto precharge is either enabled or disabled for ...
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Figure 118: READ Burst T0 CK# CK Command READ NOP Address Bank a, Col DQS DQ ...
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Figure 119: Consecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS Notes (if 4, the ...
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Figure 120: Nonconsecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS Notes (if burst is ...
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Figure 121: Random Read Accesses T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS Notes (if 4, ...
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Figure 122: Terminating a READ Burst T0 CK# CK Command 1 READ Bank a, Address Col n DQS CK Command READ Bank a, Address Col n DQS ...
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Figure 123: READ-to-WRITE T0 CK# CK Command 1 READ Bank, Address Col n DQS 3 CK# CK Command 1 READ Bank, Address Col n DQS 3 the cases shown (applies ...
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Figure 124: READ-to-PRECHARGE T0 CK# CK Command 1 READ Banka, Address Col n DQS CK# CK Command 1 READ Banka, Address Col n DQS interrupted burst ...
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Figure 125: Data Output Timing – CK# CK LDQS DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First data no longer valid) DQ[7:0] and LDQS, collectively UDQS ...
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Figure 126: Data Output Timing – DQS0/DQS1/DQS2/DQS3 4 DQ (Last data valid (First data no longer valid) DQ (Last data valid) ...
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Figure 127: Data Output Timing – CK# CK Command READ NOP DQS or LDQS/UDQS 2 All DQ values, collectively 3 Notes: 1. Commands other than NOP can be valid during this cycle transitioning after DQS transitions ...
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WRITE Operation WRITE bursts are initiated with a WRITE command, as shown in Figure 107 (page 160). The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. ...
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Data for any WRITE burst can be truncated by a subsequent PRECHARGE command, as shown in Figure 138 (page 202) and Figure 139 (page 203). Note that only the data-in pairs that are registered prior to the any subsequent data-in ...
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Figure 129: Write – DM Operation CKE Command 1 ACTIVE NOP Row Address A10 Row BA0, BA1 Bank ...
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Figure 130: WRITE Burst Command Address t DQSS (NOM) t DQSS (MIN) t DQSS (MAX uninterrupted burst shown. Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled PDF: 09005aef83ba4387 ...
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Figure 131: Consecutive WRITE-to-WRITE T0 CK Command WRITE Bank, Address Col b t DQSS (NOM) DQS Each WRITE command can be to any bank. Notes uninterrupted burst shown. ...
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Figure 133: Random WRITE Cycles T0 CK# CK 1,2 Command WRITE Bank, Address Col b t DQSS (NOM) DQS DQ 3 Each WRITE command can be to any bank. Notes: 2. Programmed ...
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Figure 134: WRITE-to-READ – Uninterrupting T0 CK Command 2,3 WRITE Bank a, Address Col DQSSnom DQSS DQS DQSSmin DQSS DQS DQSSmax DQSS ...
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Figure 135: WRITE-to-READ – Interrupting T0 CK# CK Command 1,2 NOP WRITE Bank a, Address Col DQSS (NOM) DQSS 4 DQS DQSS (MIN) DQSS 4 DQS ...
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Figure 136: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK Command 2 WRITE NOP Bank a, Address Col DQSS (NOM) DQSS 4 DQS DQSS (MIN) DQSS 4 DQS D ...