MT4LSDT864AG-10EG2 Micron Technology Inc, MT4LSDT864AG-10EG2 Datasheet - Page 20
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MT4LSDT864AG-10EG2
Manufacturer Part Number
MT4LSDT864AG-10EG2
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT4LSDT864AG-10EG2.pdf
(28 pages)
Specifications of MT4LSDT864AG-10EG2
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
168UDIMM
Device Core Size
64b
Organization
8Mx64
Total Density
64MByte
Chip Density
128Mb
Access Time (max)
6ns
Maximum Clock Rate
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
560mA
Number Of Elements
4
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
168
Mounting
Socket
Lead Free Status / Rohs Status
Not Compliant
Notes
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
22. V
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured at 1.5V with equivalent load:
f = 1 MHz; T
with minimum cycle time and the outputs open.
indicate cycle time at which proper operation over the full temperature range is
ensured (0°C ≤ T
commands, before proper device operation is ensured. (V
ered up simultaneously. V
REFRESH command wake-ups should be repeated anytime the
ment is exceeded.
sit between V
t
a reference to V
High-Z.
crossover point. If the input transition time is longer than 1ns, then the timing is ref-
erenced at V
are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency alteration for the test condition.
cannot be greater than one-third of the cycle rate. V
a pulse width ≤3ns.
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
IH
Q
is dependent on output loading and cycle rates. Specified values are obtained
specifications are tested after the device is properly initialized.
overshoot: V
DD
current will increase or decrease proportionally according to the amount of
t
CK = 10ns for -10E;
A
50pF
IL
IH
= 25°C; pin under test biased at 1.4V.
(MAX) and V
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
OH
DD
and V
A
IH
≤ +70°C for commercial,
or V
tests have V
(MAX) = V
IL
OL
IH
(or between V
. The last valid data element will meet
SS
or V
t
20
SS
T = 1ns.
IH
and V
t
t
t
.
DD
CKS; clock(s) specified as a reference only at minimum
WR plus
WR.
DD
(MIN) and no longer at the ISV crossover point.
t
IL
CK = 7.5ns for -133 and -13E.
IL
, V
Q + 2V for a pulse width ≤3ns, and the pulse width
levels.
= 0V and V
SS
DD
Q must be at same potential.) The two AUTO
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q = +3.3V;
IL
t
RP; clock(s) specified as a reference only at
and V
–
IH
40°C ≤ T
IH
= 3V, with timing referenced to 1.5V
) in a monotonic manner.
IL
A
undershoot: V
≤ +85°C for industrial).
DD
©2002 Micron Technology, Inc. All rights reserved.
and V
t
t
OH before going
REF refresh require-
DD
IL
Q must be pow-
(MIN) =
Notes
–
2V for