DAC1205D650HW/C1,5 NXP Semiconductors, DAC1205D650HW/C1,5 Datasheet - Page 19

• Manufacturer Part Number: DAC1205D650HW/C1,5
• Description: IC DAC 12BIT 650MSPS DL 100HTQFP
• Manufacturer: NXP Semiconductors

Specifications of DAC1205D650HW/C1,5

• Settling Time: 20ns
• Number Of Bits: 12
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286777518

NXP Semiconductors
DAC1205D650
Product data sheet
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Default settings are shown highlighted.
Table 20.
Table 21.
Bit
7 to 0 FREQ_NCO[23:16]
Bit
7 to 0 FREQ_NCO[31:24]
Bit
7 to 0 PH_NCO[7:0]
Bit
7 to 0 PH_NCO[15:8]
Bit
7
6
5 to 1 DAC_A_OFFSET[4:0]
Bit
7 to 6 DAC_A_GAIN_COARSE[1:0
5 to 0 DAC_A_GAIN_FINE[5:0]
Bit
7 to 6 DAC_A_GAIN_COARSE[3:2
5 to 0 DAC_A_OFFSET[10:5]
Symbol
Symbol
Symbol
Symbol
Symbol
DAC_A_PD
DAC_A_SLEEP
Symbol
]
Symbol
]
FREQNCO_UISB register (address 05h) bit description
FREQNCO_MSB register (address 06h) bit description
PHINCO_LSB register (address 07h) bit description
PHINCO_MSB register (address 08h) bit description
DAC_A_Cfg_1 register (address 09h) bit description
DAC_A_Cfg_2 register (address 0Ah) bit description
DAC_A_Cfg_3 register (address 0Bh) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 13 September 2010
Dual 12-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
R/W
R/W
Access Value Description
R/W
R/W
Access Value
R/W
R/W
-
-
-
-
0
1
0
1
-
-
-
most significant 8 bits for the NCO phase setting
-
-
upper intermediate 8 bits for the NCO
frequency setting
most significant 8 bits for the NCO frequency
setting
lower 8 bits for the NCO phase setting
DAC A power
DAC A Sleep mode
lower 5 bits for the DAC A offset
on
off
disabled
enabled
least significant 2 bits for the DAC A gain
setting for coarse adjustment
the 6 bits for the DAC A gain fine
adjustment setting
Description
most significant 2 bits for the DAC A
gain setting for coarse adjustment
most significant 6 bits for the DAC A
offset
DAC1205D650
© NXP B.V. 2010. All rights reserved.
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