AD9779BSVZ Analog Devices Inc, AD9779BSVZ Datasheet - Page 6

• Manufacturer Part Number: AD9779BSVZ
• Description: IC DAC 16BIT DUAL 1GSPS 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9779BSVZ

• Data Interface: Serial
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 1GSPS
• Input Channel Type: Parallel
• Digital Ic Case Style: QFP
• No. Of Pins: 160
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9779A-EBZ - BOARD EVALUATION FOR AD9779A
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9776/AD9778/AD9779
DIGITAL SPECIFICATIONS
T
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2. AD9776, AD9778, and AD9779 Digital Specifications
Parameter
CMOS INPUT LOGIC LEVEL
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−)
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)
DAC CLOCK INPUT (CLK+, CLK−)
SERIAL PERIPHERAL INTERFACE
1
2
3
4
Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load; maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests
using an external buffer for this signal.
Guaranteed at 25°C. Can drift above 120 Ω at temperatures above 25°C.
When using the PLL, a differential swing of 2 V p-p is recommended.
Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V.
MIN
Input V
Input V
Maximum Input Data Rate at Interpolation
Output V
Output V
Input Voltage Range, V
Input Differential Threshold, V
Input Differential Hysteresis, V
Receiver Differential Input Impedance, R
LVDS Input Rate
Set-Up Time, SYNC_I to DAC Clock
Hold Time, SYNC_I to DAC Clock
Output Voltage High, V
Output Voltage Low, V
Output Differential Voltage, |V
Output Offset Voltage, V
Output Impedance, R
Maximum Clock Rate
Differential Peak-to-Peak Voltage (CLK+, CLK−)
Common-Mode Voltage
Maximum Clock Rate
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
to T
1×
2×
4×
8×
MAX
IN
IN
OUT
OUT
Logic High
Logic Low
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V,
Logic High
Logic Low
4
O
OA
IA
OA
OS
or V
or V
or V
IB
OB
OB
IDTH
IDTHH
OD
|
− V
IDTHL
IN
2
1
3
Conditions
SYNC_I+ = V
SYNC_O+ = V
Single-ended
Rev. A | Page 6 of 56
IA
OA
, SYNC_I− = V
, SYNC_O− = V
IB
OB
, 100 Ω termination
I
OUTF
S
= 20 mA, maximum sample rate, unless
Min
2.0
300
250
200
125
2.4
825
−100
80
−0.2
1
825
1025
150
1150
80
1
400
300
1
40
Typ
20
200
100
800
400
Max
0.8
0.4
1575
+100
120
125
1575
250
1250
120
2000
500
12.5
12.5
Unit
V
V
MSPS
MSPS
MSPS
MSPS
V
V
mV
mV
mV
Ω
MSPS
ns
ns
mV
mV
mV
mV
Ω
GHz
mV
mV
GSPS
MHz
ns
ns